Light emitting diode module for surface mount technology and method of manufacturing the same

Patent No. US10217912 (titled "Light emitting diode module for surface mount technology and method of manufacturing the same") on Nov 27, 2017. The application was issued on Feb 26, 2019.

What is this patent about?

’912 is related to the field of semiconductor light-emitting diodes (LEDs), specifically focusing on flip-chip architectures designed to improve reliability and light extraction. The invention addresses technical challenges associated with leakage currents, static electricity discharge, and current crowding that often occur when reflective metal layers are placed in direct contact with semiconductor surfaces containing structural defects.

The underlying idea behind ’912 is the introduction of a defect blocking layer—a patterned insulating structure—interposed between the second semiconductor layer and the reflective electrode. By strategically masking portions of the semiconductor surface, the invention prevents the reflective metal from touching potential defect sites, thereby cutting off leakage paths. The key engineering insight is the use of a variable area ratio for the openings in this blocking layer, which allows for precise control over current injection across the device surface.

The claims of ’912 focus on a stacked LED structure featuring an insulation layer specifically shaped to expose only selective portions of the second semiconductor layer. A reflective layer is then deposited over this insulation, making electrical contact with the semiconductor exclusively through these defined openings. This configuration ensures that the reflective electrode is both an optical component and a current-injection tool that is physically separated from the majority of the semiconductor surface by the insulating barrier.

In practice, the invention utilizes a mesa structure where the active and second semiconductor layers are etched to reveal the underlying first semiconductor layer. The defect blocking layer is applied to the top of these mesas with a distribution of openings that varies spatially; for instance, the density of openings is higher in the center and lower near the edges. This gradient compensates for the natural tendency of current to crowd near the n-type contact, ensuring a uniform glow across the entire active region and preventing localized overheating.

This approach differentiates itself from prior art by moving away from continuous, direct-contact reflection layers that are prone to cracking and electrical failure. By using the defect blocking layer as a current-shaping mask, the design simultaneously improves the device's resistance to electrostatic discharge and enhances light extraction efficiency. The resulting module maintains high conductivity and optical reflectance while shielding the sensitive active layers from the metallic diffusion and stress-induced cracks typical of conventional flip-chip designs.

How does this patent fit in bigger picture?

Technical Landscape

In the early 2010s when ’912 was filed, light emitting diode (LED) architectures were typically implemented using surface-mount designs where p-type and n-type pads were positioned on the top surface of the semiconductor stack. At this time, systems commonly relied on simple insulating layers to define contact areas, which often led to current crowding at the interface between the semiconductor and the electrical pads. Furthermore, when hardware constraints required the use of metallic reflection layers for flip-chip configurations, preventing the diffusion of reflective metals into the surrounding contact structures was non-trivial, often resulting in increased resistivity and degraded reliability of the electrical connections.

Prosecution Position

The disclosed invention achieves a technical advancement in LED reliability and efficiency through a multi-layered architectural shift that integrates a patterned defect blocking layer and a specific insulating sequence. By utilizing a defect blocking layer with varying ratios of opening regions to masking regions across different zones, the system enables precise control over current distribution to mitigate leakage current and electrostatic discharge. The integration of a conductive reflection layer separated by a first insulating layer, combined with a second insulating layer and a reflection barrier, overcomes the technical constraint of metal migration. This structure ensures high conductivity at the pads while simultaneously reducing current crowding and preventing the degradation of electrical contacts caused by metallic diffusion during bonding processes.

Claims

The patent contains a total of 21 claims, with claims 1 and 14 serving as the independent claims. These independent claims focus on the structural configuration of a light emitting diode, specifically detailing a stacked semiconductor arrangement featuring an insulation layer with selective openings that allow a reflective layer or electrode to establish electrical contact with the second semiconductor layer. The dependent claims serve to further define the device by specifying material properties such as distributed Bragg reflectors, geometric variations in the opening regions, the inclusion of additional insulation layers for side surface protection, and the integration of specific metal pads and ohmic contacts to enhance electrical and optical performance.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
Exposed selective portions
(Claim 1)
The defect blocking layer may include a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio in the second region. The opening region may be formed to expose portions of the second conductive type semiconductor layer through a plurality of openings isolated from each other. This configuration reduces the probability that a leakage current and static electricity discharge occur.Specific areas of the second semiconductor layer revealed through a patterned insulation layer, often arranged in varying ratios or patterns (like concentric polygons) to prevent current crowding and leakage.
Insulation layer
(Claim 1, Claim 14)
The defect blocking layer may include an insulating layer or a distributed Bragg reflector. The forming of the insulating layer may include stacking dielectric layers having different refractive indexes. The insulation layer is patterned to form a masking region and an opening region to partially expose the top surface of the second conductive type semiconductor layer.A dielectric layer, which may include a distributed Bragg reflector (DBR) or stacked dielectric layers with different refractive indexes, patterned to selectively expose the underlying semiconductor to control current injection and block defects.
Mesa
(Claim 14)
The LED may further include a plurality of mesas each including the active layer and the second conductive type semiconductor layer. The exposed part of the first conductive type semiconductor layer is located in the peripheral region of the plurality of mesas. The mesa region is formed to expose the first semiconductor layer.A raised semiconductor stack structure created by partially removing the second semiconductor and active layers to expose the underlying first semiconductor layer, typically defining the light-emitting area.
Reflective electrode layer
(Claim 14)
A reflective electrode layer positioned over the second conductive type semiconductor layer so as to form an ohmic contact, and covering at least a part of the defect blocking layer. The reflective electrode layer forms an ohmic contact with the second conductive type semiconductor layer through the plurality of openings. In a flip-chip type, light is reflected by the reflection layer after a semiconductor layer is formed on the substrate.A multi-functional conductive layer that fills insulation openings to establish electrical contact with the mesa while simultaneously acting as a mirror to redirect light through the substrate.
Reflective layer
(Claim 1)
A reflective electrode layer is positioned over the second conductive type semiconductor layer so as to form an ohmic contact, and covering at least a part of the defect blocking layer. The plurality of openings may be filled with the reflective electrode layer. Light is reflected by the reflection layer, and a barrier layer may be provided on the reflection layer to prevent diffusion of the metal.A conductive metallic structure, also referred to as a reflective electrode layer, that forms an ohmic contact with the second semiconductor layer through openings in an insulation layer to reflect light and provide electrical bias.

Litigation Cases New

US Latest litigation cases involving this patent.

Case NumberFiling DateTitle
3:25-cv-05637Jul 22, 2025Seoul Semiconductor Co Ltd V. Bfg Supply Co Llc

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US10217912

Application Number
US15823325A
Filing Date
Nov 27, 2017
Publication Date
Feb 26, 2019
External Links
Slate, USPTO , Google Patents