Method for deriving a motion vector

Patent No. US10397613 (titled "Method for deriving a motion vector") on Jul 14, 2017. The application was issued on Aug 27, 2019.

What is this patent about?

’613 is related to the field of video decoding, specifically the management of motion vector candidates used in inter-frame prediction. In modern video compression standards, decoders improve efficiency by predicting the motion of a current block based on the movement of neighboring blocks in the same frame or co-located blocks in previously processed frames. However, maintaining a high-resolution map of every motion vector from previous frames creates a massive memory bottleneck, particularly for embedded systems with limited hardware resources.

The underlying idea behind ’613 is to implement a hardware-efficient form of buffer compression by downsampling the motion vector field of reference frames. Instead of storing or accessing a unique motion vector for every possible pixel coordinate or small sub-partition, the system applies a mathematical constraint to the coordinates used for temporal prediction. By forcing the reference coordinates through a bitwise truncation process, the decoder effectively treats a cluster of pixels as a single unit for motion data retrieval, significantly reducing the total amount of memory required to store temporal motion information.

The claims of ’613 focus on a specific method for calculating a modified reference position in a previous frame using a sequence of bitwise operations. The process involves taking an intermediate position of a current block—derived from its top-left coordinates and dimensions—and applying an arithmetic right shift followed by an arithmetic left shift, specifically by 4 units. This sequence functions as a coordinate flooring mechanism that aligns the reference point to a coarse grid, which is then used to select a temporal motion vector candidate to be merged into a list with spatial candidates from adjacent blocks.

In practice, this bitwise shifting (shifting right by 4 then left by 4) effectively zeros out the least significant bits of the coordinate values. This operation ensures that the decoder only needs to store and fetch motion vectors at 16-pixel intervals, creating a compressed motion vector buffer. When the decoder builds its candidate list for motion vector competition, it pulls from these quantized locations in the previous frame. This ensures that even if the current block is small or oddly positioned, it consistently references a predictable, grid-aligned memory address.

This approach differs from prior solutions that either stored every individual motion vector or used simple center-point sampling, both of which fail to optimize the underlying memory architecture. By utilizing the arithmetic shift sequence, the invention provides a deterministic way to reduce the resolution of the motion vector buffer without losing the essential directional data needed for accurate prediction. This allows the decoder to maintain high compression performance while operating within the strict memory bandwidth and storage limits of consumer electronics and embedded hardware.

How does this patent fit in bigger picture?

Technical Landscape

In the early 2010s when ’613 was filed, video coding architectures were characterized by a trade-off between high compression efficiency and the resulting computational and memory overhead. At a time when motion estimation was typically implemented using high-precision motion vectors, systems commonly relied on large, uncompressed memory buffers to store reference data for motion vector competition. Hardware constraints in embedded systems made the storage and rapid retrieval of these motion parameters non-trivial, as the increasing volume of data required for accurate prediction often exceeded the available on-chip memory bandwidth and capacity.

Prosecution Position

The disclosed invention addresses the technical problem of excessive memory consumption and circuit complexity in video decoders by integrating a buffer compression mechanism specifically for motion vector competition. By applying compression to the motion vector data stored in the buffer, the architecture reduces the physical memory footprint required for temporal prediction without sacrificing the accuracy of the motion estimation process. This architectural shift enables more efficient data throughput and reduces the hardware cost of the decoding system, overcoming the constraint of limited memory resources in high-efficiency video processing environments.

Claims

This patent contains a total of 14 claims, with claims 1 and 8 serving as the independent claims. The independent claims focus on a method and a corresponding decoder for deriving a motion vector of a current block by generating a candidate list that includes motion vectors from adjacent blocks in the current frame and a second motion vector derived from a modified position in a previous frame using specific arithmetic shift operations. The dependent claims serve to further define the spatial locations of adjacent blocks, specify conditions for handling intra-prediction blocks, detail the calculation of the intermediate position, and provide for the removal of duplicate candidates from the predictor list.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
Arithmetic left shift operation of 4 units
(Claim 1, Claim 8)
The modified position is derived by performing an arithmetic left shift operation of 4 units after an arithmetic right shift operation of 4 units to the intermediate position. This specific sequence of operations is used in the context of image decoding using buffer compression for motion vector competition.A bitwise operation that shifts the binary representation of a coordinate value to the left by four positions, effectively multiplying the value by 16 while maintaining the sign.
Arithmetic right shift operation of 4 units
(Claim 1, Claim 8)
The modified position is derived by performing an arithmetic left shift operation of 4 units after an arithmetic right shift operation of 4 units to the intermediate position. This operation is part of a method to reduce memory requirements for motion estimation in embedded systems.A bitwise operation that shifts the binary representation of a coordinate value to the right by four positions, effectively dividing the value by 16 and discarding the remainder.
Intermediate position
(Claim 1, Claim 8)
The intermediate position of the current block is derived by using a top-left position of the current block, a horizontal size of the current block and a vertical size of the current block. It serves as the input for the subsequent arithmetic shift operations to determine a modified position.A calculated coordinate point within or relative to the current block, determined using the block's top-left coordinates and its horizontal and vertical dimensions.
Modified position
(Claim 1, Claim 8)
The modified position is derived by performing an arithmetic left shift operation of 4 units after an arithmetic right shift operation of 4 units to the intermediate position. This modified position is used to identify the location of a second motion vector in a previous frame. This process relates to buffer compression for motion vector competition.A coordinate location in a previous frame derived by applying specific bitwise arithmetic shifts to an intermediate position of the current block to facilitate motion vector derivation.
Motion vector predictor candidate list
(Claim 1, Claim 8)
The motion vector competition (MVC) technique is used to select a motion vector predictor from a set of motion vector candidates. The candidates may include spatial motion vectors and temporal motion vectors. The decoder generates a list of these candidates to determine the most accurate predictor for the current block.A set of potential motion vector candidates, including spatial vectors from adjacent blocks and temporal vectors from a previous frame, used to select a predictor for the current block's motion vector.

Litigation Cases New

US Latest litigation cases involving this patent.

Case NumberFiling DateTitle
1:25-cv-00967Jun 23, 2025Velos Media, LLC v. ByteDance Ltd et al

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US10397613

Application Number
US15650565A
Filing Date
Jul 14, 2017
Publication Date
Aug 27, 2019
External Links
Slate, USPTO , Google Patents