Memory module with data buffering

What is this patent about?

’314 is related to the field of high-density memory modules, such as DIMMs, used in computer systems. It specifically addresses the technical challenges of increasing memory capacity and signal integrity by managing the electrical interface between a memory controller and multiple ranks of memory integrated circuits. The background context involves the physical and electrical limitations—such as capacitive loading, signal interference, and chip-select constraints—that typically arise when trying to expand memory beyond standard configurations.

The underlying idea behind ’314 is the use of an active buffering and logic layer resident on the memory module to decouple the physical memory devices from the system data bus. By implementing load isolation, the invention allows a memory module to populate more ranks or higher-density configurations than the memory controller might natively support or electrically handle. A key engineering insight is the intentional introduction of a registered data transfer delay, which provides the necessary timing budget for the logic to manage complex data path switching and address translation without compromising signal integrity at high frequencies.

The claims of ’314 focus on a memory module architecture that utilizes circuitry and logic to manage data transfers between a plurality of N-bit wide ranks and an N-bit wide data bus. The independent claims specifically cover the use of logic pipelines and control signals to enable registered data transfers through the module’s internal circuitry. A critical limitation in these claims is that the circuitry adds a predetermined time delay to these transfers, resulting in an overall CAS latency for the module that is higher than the actual operational CAS latency of the individual memory chips mounted on it.

In practice, the invention works by intercepting input address and control signals, including chip selects, and generating registered versions to activate specific memory ranks. When a read or write command is issued, the module's logic provides control signals to a buffer that selectively couples the target rank to the data bus while isolating others. This mechanism effectively masks the electrical load of the inactive ranks from the memory controller. By reporting a higher CAS latency to the system via the Serial-Presence-Detect (SPD) device, the module gains the extra clock cycles needed to perform this internal routing and signal conditioning.

This approach differs from prior solutions by moving beyond simple passive wiring or basic registering of command lines. Unlike standard registered DIMMs that only buffer control signals, this invention implements a data path rank buffer that actively manages the DQ and DQS (data strobe) lines. This prevents signal collisions during back-to-back reads from different ranks and reduces the total capacitive load seen by the memory controller to that of the buffer itself, rather than the sum of all memory chips. This allows for the transparent use of lower-density, lower-cost components to simulate high-capacity, high-performance virtual memory devices.