Motion prediction in video coding

What is this patent about?

’960 is related to the field of video compression and decompression, specifically focusing on motion-compensated prediction techniques. In modern video codecs, bi-directional prediction improves efficiency by averaging two different reference blocks to predict a current block of pixels. However, conventional methods often introduce significant rounding errors because they reduce the bit-depth of each individual prediction signal before combining them, leading to a loss of image fidelity and requiring complex signaling to manage rounding directions.

The underlying idea behind ’960 is to maintain prediction signals at a higher bit-depth throughout the intermediate calculation stages to preserve mathematical accuracy. Instead of truncating or rounding each reference block prediction to the standard pixel bit-depth immediately after interpolation, the system keeps these values in a high-precision intermediate format. By delaying the precision reduction until after the multiple prediction signals have been mathematically combined, the invention minimizes the cumulative effect of rounding noise that typically plagues multi-reference prediction.

The claims of ’960 focus on a method and apparatus that identifies a block requiring multiple reference blocks and determines specific pixel locations within those references. The system generates a first and second prediction at a second precision that is strictly higher than the original pixel bit-depth. These high-precision signals are then merged into a combined prediction, and only after this combination is the final bit-depth reduced back to the original precision through a right-shift operation.

In a practical implementation, when a motion vector points to a fractional pixel location, the encoder or decoder applies an interpolation filter to the surrounding full pixels. Rather than right-shifting the result of this filter all the way down to an 8-bit or 10-bit pixel value, the system performs a partial shift or no shift at all, storing the result in a larger register, such as a 16-bit buffer. This allows the subsequent averaging of the two blocks to occur without losing the fractional data that would have been discarded in a standard two-stage rounding process.

This approach differs from prior solutions by eliminating the need to signal rounding offsets or alternate rounding directions between frames in the bitstream. By utilizing delayed bit-depth reduction, the invention simplifies the codec architecture, as it removes the requirement for separate code branches to handle different rounding modes. The result is a more streamlined decoding process that achieves higher reconstruction quality by ensuring that the final pixel values are derived from the most accurate possible intermediate sum.