Accelerated mathematical engine

What is this patent about?

’349 is related to the field of accelerated mathematical engines, specifically hardware architectures designed to optimize the heavy computational load of convolution and deconvolution operations in neural networks. Traditional general-purpose processors often struggle with these tasks due to the overhead of constant memory fetching and the sequential nature of scalar arithmetic. The invention addresses these bottlenecks by providing a specialized hardware structure that maximizes data reuse and parallel execution.

The underlying idea behind ’349 is a two-dimensional systolic-like array of sub-circuits that performs massive parallel dot-product calculations in a single synchronized flow. By vectorizing image data and weights into specific formats that match the physical dimensions of the processor array, the system can execute thousands of multiplications and additions simultaneously. This approach minimizes the energy-intensive process of reading from SRAM by allowing a single piece of fetched data to be shared across multiple computational elements within the grid.

The claims of ’349 focus on a matrix processor architecture comprising a two-dimensional array of sub-circuits, where each sub-circuit integrates an ALU, an accumulator, and a shadow register. The independent claims specify a structure where a first input circuit feeds image data operands along one dimension while a second input circuit feeds weight operands along another. This configuration allows the hardware to convolve multiple input regions with multiple filters by cycling data through the array and capturing results without interrupting the next calculation cycle.

In practice, the invention utilizes in-line formatters to transform multi-dimensional image tensors and filter kernels into linear vectors that align with the rows and columns of the processor. A critical mechanical advantage is the use of the shadow register within each cell; this allows the accumulated result of a convolution to be stored and shifted out to the output array while the ALU immediately begins working on the next set of operands. This overlapping of computation and data transfer ensures that the mathematical engine remains at peak utilization, producing a new result every clock cycle.

This hardware-centric approach differs from prior solutions that rely on software-based matrix manipulation or standard GPU architectures that require frequent intermediate storage of partial products. By implementing booth encoders shared across rows and utilizing a clocked data-shifting mechanism, the ’349 patent reduces the managerial overhead of data movement. The result is a specialized engine that achieves higher throughput and lower power consumption by treating the convolution not as a series of discrete instructions, but as a continuous, parallelized flow of data through a dedicated physical grid.