Field Programmable Gate Array With External Phase-Locked Loop

What is this patent about?

’286 is related to the field of field-programmable gate arrays (FPGAs) , specifically addressing the challenge of synchronizing receiver and transmitter clock signals within an FPGA used in high-speed applications like high-frequency trading. Traditional solutions introduce delays due to clock domain crossing circuits, which negatively impacts processing speed. The patent aims to overcome this latency issue.

The underlying idea behind ’286 is to eliminate the need for a clock domain crossing circuit by using an external phase control loop to actively adjust the transmitter clock signal's phase to match the receiver clock signal's phase. This is achieved by feeding back the receiver and transmitter clock signals to an external phase detector and using the detected phase difference to adjust an external adjustable oscillator that drives the transmitter clock generation circuitry.

The claims of ’286 focus on a method for processing a first serial data stream (market data) to generate a second serial data stream (order entry data) using an FPGA system. The method involves receiving the market data and a reference clock signal, deserializing the data, generating a receiver-side clock, performing computations on the data, and then serializing the processed data for transmission. Crucially, the method includes an external phase control loop that adjusts the transmitter-side clock based on a comparison with the receiver-side clock, ensuring phase alignment without a clock domain crossing circuit.

In practice, the FPGA receives high-speed serial data, deserializes it into parallel streams, performs computations (e.g., a trading algorithm), and then serializes the results for transmission. The key is the external phase control circuit, which continuously monitors the phase difference between the receiver and transmitter clocks. This circuit adjusts the frequency or phase of an external oscillator, which in turn affects the transmitter clock signal. This feedback loop ensures that the transmitter clock remains synchronized with the receiver clock, allowing for direct data transfer between clock domains without the added latency of a clock domain crossing circuit.

This approach differentiates itself from prior solutions by moving the phase synchronization mechanism outside the FPGA and implementing it as a closed-loop feedback system. Instead of relying on internal clock domain crossing circuits that inherently introduce delays, ’286 uses an external phase detector, phase controller, and adjustable oscillator to actively align the transmitter and receiver clock phases. This allows for faster processing and reduced latency, which is critical in applications like high-frequency trading where even microsecond delays can have significant consequences.