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Method For Depinning The Fermi Level Of A Semiconductor At An Electrical Junction And Devices Incorporating Such Junctions

Patent No. US10937880 (titled "Method For Depinning The Fermi Level Of A Semiconductor At An Electrical Junction And Devices Incorporating Such Junctions") was filed by Oak Ip Llc on May 12, 2020.

What is this patent about?

’880 is related to the field of semiconductor devices, specifically addressing the problem of Fermi level pinning at metal-semiconductor junctions. Traditional Schottky diodes and transistors suffer from unpredictable barrier heights due to surface states and metal-induced gap states (MIGS), hindering device performance and limiting design flexibility. The patent seeks to overcome these limitations by introducing a controlled interface layer between the metal and the semiconductor.

The underlying idea behind ’880 is to depin the Fermi level of the semiconductor by interposing a thin interface layer between the metal contact and the semiconductor material. This interface layer serves a dual purpose: it passivates the semiconductor surface, eliminating dangling bonds and reducing surface states, and it provides a physical separation to minimize the influence of MIGS. By carefully controlling the composition and thickness of this interface layer, the barrier height at the junction can be tuned and made more predictable.

The claims of ’880 focus on an electrical junction comprising an interface layer between a contact metal and a source/drain region of a transistor, where the source/drain is a silicon-based semiconductor. The interface layer includes a titanium oxide spacer layer and a silicon oxide passivation layer adjacent to the semiconductor. A key feature is the thinness of the silicon oxide passivation layer, specified as less than 1 nm. Claim 28 further specifies a field-effect transistor incorporating this junction, requiring a specific contact resistivity of less than 10 Ω-μm².

In practice, the invention involves depositing a thin layer of silicon oxide onto the silicon semiconductor surface to passivate it, followed by a titanium oxide spacer layer, and then the titanium contact metal. The thinness of the silicon oxide layer is crucial to allow current flow while still passivating the surface. The titanium oxide spacer layer further reduces the effect of MIGS by increasing the distance between the metal and the semiconductor. This combination allows for a more predictable and tunable Schottky barrier height, improving transistor performance.

This approach differentiates itself from prior art by avoiding the use of silicides as contact metals, which limit material choices and fix the barrier height. Instead, ’880 allows for the selection of metals with specific work functions to tailor the barrier height, enabling the creation of devices with desired electrical characteristics. The use of a titanium oxide spacer layer in conjunction with a thin silicon oxide passivation layer is also a key differentiator, providing a balance between surface passivation, MIGS reduction, and low contact resistance.

How does this patent fit in bigger picture?

Technical landscape at the time

In the early 2000s when ’880 was filed, metal-semiconductor junctions were commonly used in electronic devices, at a time when controlling the Schottky barrier height was a significant challenge. Surface states and metal-induced gap states (MIGS) often pinned the Fermi level, making it difficult to tune the electrical properties of the junction. Achieving low specific contact resistance while also depinning the Fermi level was non-trivial due to the limitations of interface layer materials and fabrication techniques.

Novelty and Inventive Step

The examiner allowed the claims because the prior art neither disclosed nor suggested electrical junctions having an interface layer with specific characteristics. These characteristics include: a spacer layer made of titanium oxide and a semiconductor oxide passivation layer; the semiconductor oxide passivation layer having a thickness of less than 1 nm; the titanium oxide spacer layer presenting a potential barrier lower than 1 eV; and a passivation layer adjacent to the silicon-based semiconductor made of silicon oxide, with the passivation layer having a thickness of less than about 1 nm.

Claims

This patent includes 28 claims, with independent claims numbered 1, 22, 23, and 28. The independent claims generally focus on an electrical junction comprising an interface layer between a contact metal and a transistor's source or drain, with specific material compositions and properties. The dependent claims generally add further details and limitations to the electrical junction and its components, such as specific materials, dimensions, and configurations.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
Interface layer
(Claim 1, Claim 22, Claim 23, Claim 28)		“The present inventors have determined that for thin interface layers disposed between a metal and a silicon-based semiconductor (e.g., Si, SiC and SiGe), so as to form a metal-interface layer-semiconductor junction, there exist corresponding minimum specific contact resistances. The interface layer thickness corresponding to this minimum specific contact resistance will vary depending upon the materials used, however, it is a thickness that allows for depinning the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor when the junction is biased (e.g., forward or reverse biased).”A layer positioned between a contact metal and a source or drain of a transistor, affecting the electrical properties of the junction.
Passivation layer
(Claim 22, Claim 23, Claim 28)		“A further embodiment of the present invention provides for depinning the Fermi level of a semiconductor in an electrical junction through the use of an interface layer disposed between a surface of the semiconductor and a conductor. The interface layer preferably (i) is of a thickness sufficient to reduce effects of MIGS in the semiconductor, and (ii) passivates the surface of the semiconductor. As indicated above, the interface layer may include a passivating material such as a nitride, oxide, oxynitride, arsenide, hydride and/or fluoride.”A layer adjacent to the silicon-based semiconductor within the interface layer, made of an oxide of silicon, that passivates the surface of the silicon-based semiconductor.
Semiconductor oxide passivation layer
(Claim 1)		“The interface layer preferably (i) is of a thickness sufficient to reduce effects of MIGS in the semiconductor, and (ii) passivates the surface of the semiconductor. As indicated above, the interface layer may include a passivating material such as a nitride, oxide, oxynitride, arsenide, hydride and/or fluoride.”A layer within the interface layer, made of a semiconductor oxide, that passivates the surface of the silicon-based semiconductor.
Silicon-based semiconductor
(Claim 1, Claim 22, Claim 23)		“The present inventors have determined that for thin interface layers disposed between a metal and a silicon-based semiconductor (e.g., Si, SiC and SiGe), so as to form a metal-interface layer-semiconductor junction, there exist corresponding minimum specific contact resistances.”A semiconductor material that includes silicon, such as Si, SiC, or SiGe, used in the source or drain of a transistor.
Spacer layer
(Claim 1, Claim 22, Claim 28)		“The interface layer may include a passivating material (e.g., a nitride, oxide, oxynitride, arsenide, hydride and/or fluoride) and sometimes also includes a separation layer. In some cases, the interface layer may be essentially a monolayer (or several monolayers) of a semiconductor passivating material.”A layer within the interface layer, specifically an oxide of titanium, that contributes to the electrical characteristics of the junction.

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US10937880

OAK IP LLC
Application Number
US15929592
Filing Date
May 12, 2020
Status
Expired
Expiry Date
Aug 12, 2022
External Links
Slate, USPTO, Google Patents