Memory module with controlled byte-wise buffers

What is this patent about?

’339 is related to the field of high-density memory subsystems, specifically focusing on the architecture of dual in-line memory modules (DIMMs) used in servers and high-performance computing. It addresses the physical and electrical limitations encountered when increasing memory capacity, where adding more DRAM chips typically creates excessive electrical loading and signal degradation on the data bus, ultimately forcing a reduction in system clock speeds.

The underlying idea behind ’339 is to decouple the heavy electrical load of multiple memory ranks from the main system bus by using a distributed buffering architecture. Instead of a single, massive central buffer that creates routing bottlenecks, the invention employs multiple small, byte-wise buffers placed strategically near their respective DRAM groups. This allows the memory controller to see only the load of a single buffer per data path, regardless of how many physical memory ranks are actually populated on the module.

The claims of ’339 focus on a memory module architecture featuring a module controller and a plurality of distributed buffers that manage data flow for multiple N-bit-wide ranks. The independent claims specifically protect the use of tristate buffers within these distributed components to actively drive data during specific time windows defined by CAS latency. This mechanism ensures that only the targeted rank is electrically connected to the data bus during a read or write operation, while all other ranks remain isolated.

In practice, the module controller acts as the brain, receiving high-level commands and translating them into localized module control signals. These signals tell the distributed byte-wise buffers exactly when to open their data paths and in which direction. By using bit slicing, the module handles data in manageable segments, such as 8-bit bytes, which allows for tighter timing control and better signal integrity across the PCB compared to traditional unbuffered or centrally buffered designs.

This approach differentiates itself from prior 'fly-by' architectures by eliminating the massive RC load that usually slows down multi-rank modules. Unlike standard LRDIMMs that might use a single large buffer, this distributed load-reduction strategy minimizes trace lengths between the buffers and DRAMs. This restores the signal waveform shapes and enables the memory to operate at higher frequencies and densities without the 'dead cycles' or collisions typically associated with heavily loaded memory channels.