Multi-Core Computer Systems With Private/Shared Cache Line Indicators

What is this patent about?

’410 is related to the field of cache coherence in multiprocessor systems, particularly those employing clustered cache hierarchies. Modern processors often group cores and their caches into clusters to reduce network congestion and improve scalability. However, maintaining cache coherence across these clusters introduces complexity, especially with traditional invalidation-based protocols that require extensive signaling.

The underlying idea behind ’410 is to simplify cache coherence in clustered systems by recognizing that data can be shared entirely within a cluster while remaining private from the perspective of other clusters. This is achieved by determining a common shared level (CSL) for each data block, which represents the highest level in the cache hierarchy where the block is shared within a cluster. By identifying this level, coherence operations can be localized, reducing the need for complex recursive protocols.

The claims of ’410 focus on a computer system with multiple processor cores and a clustered cache memory hierarchy. Each cache line includes a bit indicating whether it is private or shared. A key aspect is identifying the CSL for a memory block, based on where sharing occurs between cores. The CSL dictates which cache coherence operation is selected and performed when a coherence event arises, effectively tailoring the coherence protocol based on the data's sharing scope.

In practice, the invention involves tracking the CSL for each data block (or page) and using this information to optimize coherence operations. When a core attempts to access a data block, the system determines the CSL and then applies coherence mechanisms (like self-invalidation or write-through) only within the cluster defined by that CSL. This localization reduces the overhead associated with maintaining coherence across the entire system.

This approach differs from prior solutions that often rely on complex hierarchical directory protocols, which require intermediate nodes to behave both as root and leaf caches, leading to a large number of states and increased implementation complexity. By encapsulating the hierarchical complexity into the simple function of determining the CSL, ’410 enables the use of simpler coherence mechanisms, such as self-invalidation and write-through , but restricts their operation to the scope defined by the CSL, resulting in a more efficient and scalable coherence protocol.