Network Server Systems, Architectures, Components And Related Methods

What is this patent about?

’350 is related to the field of server systems, particularly those employing hardware acceleration for improved performance. Modern data centers often require processing large volumes of data, and traditional CPU-based servers can become bottlenecks. Hardware accelerators, such as FPGAs, are increasingly used to offload specific tasks from the main processor, improving overall system throughput and efficiency. This patent addresses the need for a flexible and scalable architecture for integrating hardware accelerators into server systems.

The underlying idea behind ’350 is to create a heterogeneous computing environment within a server by integrating a hardware acceleration module alongside the host processor. This module contains multiple computing elements, each with its own processing circuits, memory, and a data transfer fabric. The key insight is to enable these computing elements to communicate efficiently with each other and with the host processor, allowing for flexible task distribution and pipelined processing. A scheduler circuit prioritizes packet processing, enabling quality of service.

The claims of ’350 focus on a server comprising a host processor and at least one physically separate hardware acceleration (hwa) module. The hwa module includes a network interface configured to virtualize functions by redirecting network packets to different addresses within the hwa, at least one computing element formed thereon, the at least one computing element including processing circuits configured to execute a plurality of processes including at least one virtualized function, a scheduler circuit configured to allocate a priority to a processing of packets of one flow over those of another flow by the processing circuits, first memory circuits, second memory circuits, and a data transfer fabric configured to enable data transfers between the processing circuits and the first and second memory circuits; wherein the at least one computing element is configured to transfer data to, or receive data from, any of: the processing circuits, the first memory circuits, the second memory circuits, or other computing elements coupled to the data transfer fabric.

In practice, the invention allows for a server to dynamically allocate tasks to either the host processor or the hardware acceleration module based on the specific requirements of the application. For example, computationally intensive tasks like data encryption or video transcoding can be offloaded to the hardware accelerator, freeing up the host processor for other tasks. The data transfer fabric within the hardware acceleration module facilitates efficient communication between the different computing elements, enabling pipelined processing where data flows seamlessly from one element to the next.

This approach differs from traditional server architectures where hardware accelerators are typically treated as fixed-function devices. By providing a flexible and programmable hardware acceleration module with its own memory and communication infrastructure, ’350 enables a more adaptable and efficient server system. The virtualized network interface allows for dynamic redirection of network packets to different processing elements within the HWA, further enhancing flexibility and enabling the implementation of complex network functions directly on the hardware accelerator.