Chip Package
Patent No. US11107768 (titled "Chip Package") was filed by Piccadilly Patent Funding Llc As Security Holder on Jan 26, 2020.
What is this patent about?
’768 is related to the field of microelectronic packaging, specifically addressing challenges in creating high-density interconnections between integrated circuits (ICs) and other components. The background acknowledges the trend towards miniaturization and the increasing importance of metal connections, which can negatively impact performance due to parasitic capacitance and resistance. Flip-chip technology is mentioned as an existing solution, but it faces challenges in pre-testability, inspection, and thermal expansion matching. Glass interposers are considered as a substitute for silicon, offering cost advantages and CTE matching, but with limitations in thermal conductivity and through-glass via formation.
The underlying idea behind ’768 is to use a polymer layer with embedded copper plugs as a foundation for a chip package. This polymer layer acts as an interposer, providing electrical connections between a semiconductor chip and other components. The copper plugs, formed within through-vias in the polymer, serve as vertical interconnects. Metal interconnects are then patterned on top of the polymer layer, connecting to the copper plugs and forming a redistribution layer (RDL). Finally, metal bumps are added for external connections.
The claims of ’768 focus on a chip package comprising a polymer layer with specific thickness and coefficient of thermal expansion, copper plugs in through-vias , a metal interconnection scheme on the polymer surface, and metal bumps for external connections. Claim 1 details a single semiconductor chip connected to the interconnection scheme. Claim 16 expands on this, describing a configuration with two semiconductor chips, one above and one below the interconnection scheme, with the top chip connected via metal bumps and including CPU and GPU circuit blocks.
The implementation involves forming the polymer layer, creating through-vias, and filling them with copper to form the plugs. A metal interconnect scheme is then built on top of the polymer, connecting to the copper plugs. This scheme uses multiple metal layers separated by a polymer layer, allowing for complex routing. Finally, metal bumps are added to the top of the structure, providing a means to connect the chip package to other components or boards. A key aspect is the controlled coefficient of thermal expansion of the polymer layer, which helps to minimize stress and improve reliability.
This approach differs from traditional flip-chip packaging by using a polymer interposer with copper plugs instead of solder bumps directly on the chip. It also differs from glass interposers by using a polymer material, which may offer advantages in terms of cost and ease of processing. The use of a redistribution layer on top of the polymer allows for more flexible routing and higher density interconnections compared to simpler packaging methods. The multi-chip configuration described in claim 16 enables the integration of different functionalities (CPU and GPU) within a single package, improving performance and reducing size.
How does this patent fit in bigger picture?
Technical landscape at the time
In the early 2010s when ’768 was filed, at a time when microelectronic devices were being minimized and thinned, systems commonly relied on flip-chip packages to meet the increasing demands for high performance and increased Input/Output (IO). At that time, challenges remained in pre-testability, post-bonding visual inspection, and matching the Temperature Coefficient of Expansion (TCE) to avoid solder bump fatigue.
Novelty and Inventive Step
The examiner approved the application because the closest prior art does not disclose, either alone or in combination, the specific material and structure limitations of the claimed chip package, particularly the formation of a polymer interconnect with a sufficient coefficient of expansion to enable holes and other features with improved chemical durability, strength, and optical properties.
Claims
This patent includes 28 claims, with independent claims 1 and 16. The independent claims are directed to chip packages comprising polymer layers, metal plugs, interconnection schemes, and semiconductor chips. The dependent claims generally elaborate on specific features, materials, and configurations of the chip package components described in the independent claims.
Key Claim Terms New
Definitions of key terms used in the patent claims.
Patent Family
File Wrapper
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Date
Description
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US11107768
- Application Number
- US16752650
- Filing Date
- Jan 26, 2020
- Status
- Granted
- Expiry Date
- Oct 10, 2033
- External Links
- Slate, USPTO, Google Patents