Field Programmable Gate Array With External Phase-Locked Loop

What is this patent about?

’305 is related to the field of field-programmable gate arrays (FPGAs) , specifically addressing the challenge of synchronizing receiver and transmitter clock signals within the FPGA. Traditional approaches introduce delays due to clock domain crossing circuits, which is undesirable in high-speed applications like high-frequency trading where microsecond-level accuracy is crucial.

The underlying idea behind ’305 is to eliminate the need for a clock domain crossing circuit by using an external phase control circuit to actively adjust the transmitter clock signal's phase. This is achieved by comparing the receiver and transmitter clock phases, generating adjustment information, and using an adjustable oscillator to modify the transmitter clock signal until it is phase-aligned with the receiver clock.

The claims of ’305 focus on a field programmable gate array system comprising an FPGA and an external phase control circuit. The FPGA includes a deserializer to convert a serial data stream into parallel data streams and generate a receiver-side clock, computational circuitry to process the parallel data, and a serializer to convert the processed parallel data back into a serial data stream and generate a transmitter-side clock. The external phase control circuit compares the receiver and transmitter clock phases and adjusts the transmitter clock signal.

In practice, the FPGA receives a serial data stream and a reference clock signal. The deserializer converts the serial data into parallel streams and generates a receiver-side clock. The computational circuitry processes the data without clock domain crossing. The serializer converts the processed data back to serial form, generating a transmitter-side clock. The external phase control circuit, including a phase detector, phase controller, and adjustable oscillator, continuously monitors and adjusts the transmitter clock's phase to match the receiver clock's phase, ensuring phase alignment .

This approach differs from prior solutions by moving the phase synchronization mechanism outside the FPGA , thereby avoiding the inherent latency associated with on-chip clock domain crossing circuits. By using an external adjustable oscillator and a feedback loop, the system dynamically adjusts the transmitter clock signal to maintain phase alignment with the receiver clock signal, enabling faster processing and reduced latency, which is critical for applications requiring high-speed data processing and minimal delay.