System And Method For Self-Invalidation, Self-Downgrade Cachecoherence Protocols

What is this patent about?

’464 is related to the field of cache coherence in multiprocessor systems. Modern computer systems often employ multiple cores, each with its own local cache, to improve performance. However, this introduces the challenge of maintaining data consistency across these caches, ensuring that all cores see a consistent view of memory. Traditional cache coherence protocols rely on explicit invalidation or updating mechanisms, which can generate significant signaling overhead, especially as the number of cores increases.

The underlying idea behind ’464 is to use data-race detection to trigger self-invalidation of cache lines, eliminating the need for explicit invalidation messages. Instead of proactively tracking which cores have copies of a particular data block, the system detects when a potential data race occurs (i.e., a read after a write to the same memory location by different cores) and then invalidates the local cache of the reading core. This approach simplifies the coherence protocol and reduces communication overhead.

The claims of ’464 focus on a method and system where a core, upon experiencing a cache miss, checks a read-after-write detection structure to determine if a race condition exists for the requested memory block. If a race is detected, the core enforces program order between older and younger loads relative to the racing load and self-invalidates one or more cache lines in its local cache. This ensures that the core sees a consistent view of memory without requiring explicit invalidation messages from other cores.

In practice, the system employs a RAW race detector , implemented as a signature-based table, to track store operations performed by each core. When a core attempts to load data and misses in its local cache, the system checks the RAW race detector to see if another core has written to that memory location since the last time the requesting core detected a race. If a race is detected, the requesting core invalidates its cache and re-fetches the data, ensuring consistency.

This approach differs from prior solutions that rely on software to explicitly expose synchronization points or insert fence instructions. ’464 provides an implicit self-invalidation mechanism that automatically detects data races during program execution and triggers self-invalidation accordingly. This eliminates the need for software cooperation and simplifies the development of multithreaded applications, while still maintaining memory consistency.