Patent No. US11196678 (titled "Qos Manager For System On A Chip Communications") was filed by Tesla Inc on Oct 24, 2019.
’678 is related to the field of System-on-Chip (SoC) architecture, specifically addressing the challenge of managing communication between different processing systems within the SoC that operate under disparate Quality of Service (QoS) rules. Modern SoCs integrate diverse processing cores, each potentially designed with its own QoS requirements for data transfer. This heterogeneity can lead to inefficiencies, data loss, or delays when these systems need to communicate.
The underlying idea behind ’678 is to introduce a QoS manager within the SoC's channel circuitry. This manager acts as an intermediary, dynamically adjusting communication resource allocation (specifically, buffer sizes) in the receiving processing system based on the QoS requirements of the transmitting system. The key insight is to translate QoS levels between different systems, ensuring compatibility and efficient data transfer even when the native QoS rules are mismatched.
The claims of ’678 focus on a SoC comprising multiple processing systems, each with its own QoS rules, and channel circuitry that includes a QoS manager. The independent claims cover scenarios where the QoS manager determines that a first processing system wants to send data to a second processing system with different QoS rules. The manager then determines available resources in the receiving system, calculates a resource allocation based on both sets of QoS rules and the sender's QoS selection, and directs the receiver to adjust its buffer allocation accordingly. The claims also cover the reverse scenario, where the manager monitors receiver resources and directs the transmitter.
In practice, the QoS manager monitors the communication requests and available resources of the various processing systems. When a data transfer is initiated, the manager determines the QoS level requested by the sending system and translates this into an appropriate resource allocation for the receiving system. This translation might involve subdividing the receiver's buffers to match the sender's QoS levels, ensuring that high-priority data gets preferential treatment. The manager can also monitor buffer fill levels and adjust transmission rates to prevent overflow or starvation.
This approach differs from prior solutions by actively managing and translating QoS levels between processing systems, rather than relying on static resource allocation or simple prioritization schemes. By dynamically adjusting buffer sizes and transmission rates, the QoS manager optimizes communication efficiency and prevents bottlenecks caused by mismatched QoS requirements. This allows for easier integration of diverse processing cores into a single SoC, improving overall system performance and flexibility. The dynamic buffer allocation based on QoS translation is a key differentiator.
In the late 2010s when ’678 was filed, SoCs were increasingly integrating heterogeneous processing elements, at a time when inter-processor communication was typically implemented using shared memory or dedicated interconnects. When hardware or software constraints made efficient QoS management non-trivial, systems commonly relied on static resource allocation rather than dynamic adaptation to varying communication demands.
The examiner allowed the claims because the prior art, individually or in combination, failed to teach or suggest a system on a chip where a first QoS selection indicates a QoS level associated with different buffer allocations, and where the communication resource allocation translates the first QoS selection between the first and second QoS rules, causing adjustment of at least one buffer of the second processing system.
This patent contains 25 claims, of which claims 1, 8, 15, and 20 are independent. The independent claims are directed to a system on a chip (SoC) and methods for operating a system on a chip, focusing on quality of service (QoS) management between processing systems. The dependent claims generally elaborate on the features and functionalities described in the independent claims, providing more specific details and implementations.
Definitions of key terms used in the patent claims.
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