System And Method For Dynamic Enforcement Of Store Atomicity

What is this patent about?

’485 is related to the field of multiprocessor computer architecture, specifically addressing the problem of maintaining store atomicity in systems employing out-of-order execution and store buffers. Modern processors use store buffers to allow cores to continue executing instructions without waiting for stores to be globally visible, which can lead to violations of memory consistency models like Total Store Order (TSO). The patent addresses the challenge of dynamically enforcing store atomicity to ensure program correctness without unduly sacrificing performance.

The underlying idea behind ’485 is to dynamically track potential store atomicity violations arising from store-to-load forwarding . When a core forwards a store from its store buffer to a load, subsequent loads on that core are marked as potentially speculative. This speculation is maintained until the forwarded store becomes globally visible. If, during this speculative period, a younger load experiences a coherence invalidation or cache eviction, it is squashed and re-executed, preventing potential memory ordering violations.

The claims of ’485 focus on a computer system with multiple processor cores, each having a local cache and a store buffer. A key aspect is that a load on a core receiving data from a store in its store buffer temporarily prevents younger loads from committing. Furthermore, if a younger load's address is invalidated or evicted from the cache during this period, the load is squashed. The claims also cover a method for dynamic enforcement of store atomicity, involving executing a load, receiving data from a store buffer, and assigning a speculative state to subsequent loads to prevent premature commitment.

In practice, the invention introduces a new type of speculation called Store-Atomicity Speculative (SA-Speculative). A load becomes SA-Speculative if an older load (in program order) is performed via store-to-load forwarding. The load that receives the forwarded value is not speculative itself, but it makes all subsequent loads potentially speculative. This SA-Speculative state persists until the forwarded store is globally performed. The system uses identifier keys to link stores in the store buffer with a commit gate in the load queue, preventing younger loads from committing until the store is ordered.

This approach differs from prior solutions that treat all loads bypassing unperformed stores as speculative. ’485 only marks loads as speculative when a potential store atomicity violation is detected, minimizing performance overhead. The patent also describes mechanisms for handling squashes, including bulk and on-demand identifier key resets , to ensure that stale keys do not interfere with correct execution. By dynamically enforcing store atomicity only when necessary, the invention provides a more efficient way to maintain memory consistency in out-of-order processors.