Methods For Producing A 3D Semiconductor Memory Device And Structure

What is this patent about?

’214 is related to the field of 3D integrated circuits , specifically focusing on the fabrication of 3D memory devices. The background involves the increasing demand for higher memory density and performance, which traditional 2D scaling struggles to meet. 3D integration offers a solution by stacking multiple layers of memory cells vertically, but this presents challenges in manufacturing and thermal management.

The underlying idea behind ’214 is to create a 3D memory device by sequentially building multiple levels of memory cells above a base layer containing transistors and metal interconnects. This is achieved through controlled etching and deposition processes, allowing for the creation of vertically stacked memory cells with individual memory transistors in each level. The process aims to maximize memory density while maintaining manufacturability.

The claims of ’214 focus on a method for producing a 3D memory device. The method involves providing a base level with a single crystal layer and transistors, then forming subsequent levels above it. Each level is etched to create holes, and memory cells are formed within these levels, each cell having its own memory transistor. The claims also cover adjusting the annealing of the base transistors to account for the thermal budget of the memory transistor processing, and forming tungsten vias through the stacked levels.

In practice, the invention involves a layer-by-layer fabrication process. A base layer containing transistors and metal interconnects is created. Then, additional layers are formed on top, with each layer etched to create openings for memory cells. Memory transistors are then formed within these openings. The process is repeated to create multiple levels of memory cells, increasing the overall memory density. The use of single crystal silicon for the transistor channels ensures high performance.

’214 differentiates itself from prior approaches by focusing on a sequential, layer-by-layer fabrication process that allows for precise control over the formation of memory cells in each level. This approach enables the creation of high-density 3D memory devices while addressing thermal management concerns through thermal budget considerations during transistor annealing. The use of tungsten vias provides reliable electrical connections between the stacked layers.