3D Semiconductor Device And Structure With Metal Layers

What is this patent about?

’181 is related to the field of three-dimensional (3D) integrated circuits (ICs) and their fabrication. The background acknowledges that traditional device scaling is slowing, and that 3D ICs, where active layers of transistors are stacked vertically, offer a path to improved performance, lower power consumption, and higher density. Prior approaches to 3D ICs, such as bonding two pre-fabricated ICs with through-silicon vias (TSVs), suffer from limited TSV density and handling difficulties with thinned wafers. Monolithic 3D integration, where transistors are built directly on top of each other, faces challenges related to maintaining the reliability of underlying metallization during high-temperature transistor processing.

The underlying idea behind ’181 is to create a 3D IC by stacking transistor layers, where each layer contains transistors with single-crystal silicon channels. The layers are interconnected using vias with a diameter less than 500 nm . A key aspect is providing power or ground to the upper transistor layers through the existing metal layers of the lower level. This allows for a compact and efficient power distribution network within the 3D structure.

The claims of ’181 focus on a 3D semiconductor device comprising a first level with single-crystal silicon transistors and multiple metal layers, and a second level with additional transistors. The key elements are the connective path between the top metal layer of the second level and the metal layers of the first level, implemented as a via with a diameter between 5 nm and 500 nm. The claims specify that the third metal layer of the first level provides power or ground to the second-level transistors. Some claims specify the relative thickness of metal layers, the connection of multiple transistors to the third metal layer, the arrangement of transistors in a NAND gate configuration, the vertical orientation of transistors, or the use of metal gates in the second-level transistors.

In practice, the invention involves fabricating a first layer of transistors on a single-crystal silicon substrate, along with multiple metal interconnect layers. A second layer of transistors is then fabricated on top of the first layer, also using single-crystal silicon channels. The small-diameter vias provide a high-density interconnect between the two layers, allowing signals and power to be routed efficiently. The use of single-crystal silicon channels in both layers ensures high transistor performance.

This approach differentiates itself from prior art by using a monolithic fabrication process to create multiple layers of single-crystal silicon transistors, interconnected by small vias. Unlike TSV-based approaches, this allows for a much higher interconnect density. By providing power and ground through the existing metal layers, the design avoids the need for dedicated power routing structures in the upper layers, further increasing density and simplifying the fabrication process. The use of single-crystal silicon channels addresses the performance limitations of transistors fabricated using alternative silicon formation methods like selective epitaxy or laser recrystallization.