3D Semiconductor Device And Structure With Metal Layers

What is this patent about?

’599 is related to the field of three-dimensional integrated circuits (3D-ICs), specifically addressing challenges in power distribution and heat management within these multi-layered devices. Traditional 2D ICs face performance limitations due to increasing wire lengths as transistor density scales. 3D stacking offers a solution by reducing interconnect distances, but introduces new problems related to heat dissipation and efficient power delivery to multiple active layers.

The underlying idea behind ’599 is to optimize the power distribution network in a 3D-IC by using a thick, global power grid in the uppermost metal layer and connecting it to lower metal layers via small vias. This approach aims to reduce power losses and improve voltage stability across the stacked device layers. The key insight is that a thicker metal layer provides lower resistance for the global power distribution, while small vias minimize the area consumed by vertical interconnects.

The claims of ’599 focus on a semiconductor device comprising a first silicon layer with transistors, multiple metal layers, and a second level with transistors stacked above. The key features include a connection path from a fifth metal layer (global power grid) to a second metal layer via a via with a diameter less than 450 nm. The fifth metal layer, acting as the global power distribution grid, has a thickness at least 50% greater than the second metal layer. Some claims specify that the second level comprises an array of memory cells.

In practice, this architecture allows for a more robust power supply to the transistors in the stacked layers. The thicker, upper-level metal layer acts as a low-impedance power rail, minimizing voltage drops and ensuring stable operation. The small vias provide a dense interconnect between the global power grid and the lower metal layers, enabling efficient power delivery to the active devices. This is particularly important for memory arrays, where stable voltage levels are critical for reliable data storage and retrieval.

This design differentiates itself from prior approaches by strategically placing a high-conductivity global power grid in the uppermost metal layer and connecting it to lower layers using small vias. Traditional 3D-ICs may have used power distribution networks with uniform metal layer thicknesses or relied on through-silicon vias (TSVs) for vertical interconnects. TSVs, while effective, consume significant area. By using a thicker metal layer for the global power grid and small vias, ’599 achieves a balance between low power loss and high interconnect density, improving overall device performance and efficiency.