Chip Package

Patent No. US11538763 (titled "Chip Package") was filed by Piccadilly Patent Funding Llc As Security Holder on Jul 11, 2021.

What is this patent about?

’763 is related to the field of display technology and microelectronic packaging, specifically addressing the challenges of miniaturization and high-density interconnections in display devices. The background acknowledges the trend towards thinner and smaller microelectronic devices, highlighting the increasing importance of metal connections and their impact on circuit performance due to parasitic capacitance and resistance. Flip-chip technology is mentioned as an existing solution, but challenges remain in pre-testability, visual inspection, and thermal expansion matching.

The underlying idea behind ’763 is to use a glass substrate with through-glass vias (TGVs) as an interposer to bridge between integrated circuit chips and a display panel. The key insight is to leverage the advantages of glass, such as its lower material cost and CTE matching to silicon, to create a high-density interconnection platform. This involves forming metal plugs within the glass substrate to provide electrical pathways for connecting components on either side of the substrate.

The claims of ’763 focus on a chip package comprising a solid layer of silicon and oxygen (glass) with copper plugs in through vias. The claims specify dimensions (100-300 micrometers thickness), material composition, and the arrangement of the copper plugs in relation to the edge of the solid layer. The claims also cover interconnection schemes on both surfaces of the glass substrate, including metal interconnects, polymer layers, and metal bumps for connecting to semiconductor chips.

The implementation involves creating a glass substrate with embedded metal plugs that act as vertical interconnects. This is achieved through processes like forming metal traces within a glass matrix and then slicing the matrix into individual substrates. The metal plugs are then connected to metal interconnects on both the top and bottom surfaces of the substrate, allowing for the mounting of chips and other components. The use of a polymer layer over the metal interconnects provides insulation and mechanical support.

This approach differentiates itself from traditional flip-chip packaging by using a glass interposer with TGVs instead of ceramic or plastic. The close proximity of the metal plugs to the edge of the glass substrate (less than 100 micrometers) enables the creation of near-borderless displays . The use of copper plugs and copper interconnects aims to minimize resistance and improve signal integrity. The ability to mount components on both sides of the glass substrate further increases the integration density and functionality of the chip package.

How does this patent fit in bigger picture?

Technical landscape at the time

In the early 2010s when ’763 was filed, microelectronic devices were being minimized and thinned, and semiconductor packages mounted on motherboards were following this trend to realize high integration. At a time when the geometric dimensions of integrated circuits were being scaled down, metal connections connecting the integrated circuit to other circuit or system components were becoming relatively more important. Flip-chip technology was being developed to fabricate bumps on chips and interconnect them directly to the package media.

Novelty and Inventive Step

The examiner allowed the claims because the closest prior art does not disclose, either alone or in combination, the specific material and structure of the chip package, particularly the polymer interconnect with a sufficient coefficient of expansion that enables holes and other features to be formed inside with improved chemical durability, strength, and optical properties. The dependent claims were also allowable because they depend on the allowable independent claims and incorporate their limitations.

Claims

There are 23 claims in total. Claims 1 and 18 are independent. The independent claims are directed to a chip package comprising a solid layer, metal plugs or conductors, interconnection schemes, and a semiconductor chip. The dependent claims generally add further details, features, or components to the chip package described in the independent claims.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
Copper plugs
(Claim 1)
“To solve this problem, the approach has been taken to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines.”Metallic plugs made of copper, located within through vias in the second region of the solid layer.
First interconnection scheme
(Claim 1, Claim 18)
“Increased Input-Output (IO) combined with increased demands for high performance, and then IC's has led to the development of flip-chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads of chip and interconnects the bumps directly to the package media, which are usually ceramic or plastic based.”An interconnection scheme located over the first surface of the solid layer, comprising a first metal interconnect and a first polymer layer.
First metal bump
(Claim 1)
“Increased Input-Output (IO) combined with increased demands for high performance, and then IC's has led to the development of flip-chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads of chip and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path.”A metal bump located over the first interconnection scheme, comprising a second metal layer and a tin-containing layer.
Metal conductors
(Claim 18)
“To solve this problem, the approach has been taken to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines.”Metallic conductors located in the second region of the solid layer, each comprising a copper portion and a first metal layer covering a sidewall of the copper portion.
Solid layer
(Claim 1, Claim 18)
“Embodiments of the present disclosure provide A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.”A layer composed of a silicon and oxygen compound, having a thickness between 100 and 300 micrometers, and having a first region and a second region between the first region and an edge of the solid layer.

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US11538763

PICCADILLY PATENT FUNDING LLC AS SECURITY HOLDER
Application Number
US17372459
Filing Date
Jul 11, 2021
Status
Granted
Expiry Date
Sep 25, 2033
External Links
Slate, USPTO, Google Patents