Field Programmable Gate Array With External Phase-Locked Loop

What is this patent about?

’381 is related to the field of field-programmable gate arrays (FPGAs) , specifically addressing the challenge of synchronizing receiver and transmitter clock signals within the FPGA to minimize latency. Traditional FPGAs often employ clock domain crossing (CDC) circuits to achieve this synchronization, but these circuits introduce undesirable delays, particularly problematic in high-frequency trading applications where microsecond-level accuracy is crucial.

The underlying idea behind ’381 is to eliminate the need for a clock domain crossing circuit by actively phase-aligning the receiver and transmitter clock signals. This is achieved by using an external phase control circuit that monitors the phase difference between the receiver and transmitter clocks and adjusts the transmitter clock's phase to match the receiver clock's phase. This adjustment is performed outside the FPGA, minimizing latency within the FPGA's processing path.

The claims of ’381 focus on a method for processing a serial data stream using an FPGA system to generate a second serial data stream, comprising the steps of receiving a clock signal and the first serial data stream by a deserializer, generating a receiver side clock signal, converting the first serial data stream into parallel data streams, transmitting the parallel data streams to computational circuitry, transmitting the receiver side clock signal to an external phase-locked loop, generating a second clock signal using the phase-locked loop, generating a transmitter side clock signal derived from the second clock signal, performing operations on the parallel data streams to generate a second set of parallel data streams, and transmitting the second serial data stream derived from the second set of parallel data streams, without using clock domain crossing operations .

In practice, the invention involves feeding a reference clock signal into the FPGA, where a deserializer converts incoming serial data into parallel streams and generates a receiver-side clock. Simultaneously, an external phase control circuit, including a phase detector and adjustable oscillator, monitors and adjusts the transmitter-side clock. The phase detector compares the receiver and transmitter clock phases, and the phase controller uses this information to adjust the adjustable oscillator, which in turn influences the transmitter clock signal. This feedback loop ensures that the transmitter and receiver clocks are phase-aligned, enabling direct data transfer between clock domains without the latency penalty of a CDC circuit.

This approach differs significantly from prior solutions that rely on internal clock domain crossing circuits within the FPGA. By moving the phase alignment mechanism outside the FPGA and employing a feedback loop to actively synchronize the clocks, ’381 achieves a significant reduction in latency . This is particularly beneficial in applications like high-frequency trading, where even small delays can have a substantial impact on performance. The external phase control allows for fine-grained adjustment of the transmitter clock, ensuring optimal synchronization and minimizing the need for complex and time-consuming clock domain crossing procedures.