IP Verse

3D Memory Devices And Structures With Control Circuits

Patent No. US11621240 (titled "3D Memory Devices And Structures With Control Circuits") was filed by Monolithic 3D Inc on Sep 21, 2022.

What is this patent about?

’240 is related to the field of 3D integrated circuits , specifically focusing on stacking a memory level on top of a control circuit level. The background involves addressing the limitations of traditional 2D IC scaling, where interconnect performance degrades. 3D stacking offers a solution by reducing wire lengths and improving overall IC performance. Existing techniques include through-silicon vias (TSVs) and monolithic 3D technology, but ’240 explores a specific bonding and arrangement strategy.

The underlying idea behind ’240 is to create a 3D memory device by bonding a memory array directly onto a control circuit layer. This is achieved through a combination of oxide-to-oxide and metal-to-metal bonding. A key aspect is the physical arrangement, where at least one memory cell is positioned directly above a metal-to-metal bonding region. This arrangement aims to minimize interconnect distances and improve signal integrity between the control circuits and the memory cells.

The claims of ’240 focus on a semiconductor device with a control circuit level bonded to a memory level . The bonding utilizes both oxide-to-oxide and metal-to-metal regions. Claim 1 emphasizes the spatial relationship between memory cells and metal bonding regions. Claim 8 highlights the direct connection between word-lines and metal bonding regions. Claim 15 specifies independent control of at least four sub-arrays within the memory level.

In practice, the invention involves fabricating a control circuit layer with transistors and metal interconnects, and a separate memory layer with an array of memory cells. These two layers are then bonded together using a process that creates both oxide-to-oxide and metal-to-metal bonds. The placement of memory cells directly above metal bonding regions is a design consideration to optimize electrical connections. The independent control of sub-arrays allows for more granular memory management and potentially improved performance.

This approach differs from prior solutions by emphasizing the direct spatial relationship between memory cells and metal bonding regions. While other 3D stacking techniques exist, ’240's specific bonding strategy and arrangement aim to create a more efficient and compact 3D memory device. The independent control of sub-arrays also provides a level of flexibility in memory management that may not be present in other 3D memory architectures. The use of both oxide and metal bonding provides mechanical stability and good electrical contact.

How does this patent fit in bigger picture?

Technical landscape at the time

In the mid-2010s when ’240 was filed, 3D stacking of semiconductor devices was an active area of development at a time when TSV and monolithic 3D technologies were competing approaches. At a time when interconnect performance was a major constraint, 3D stacking was seen as a way to reduce wire lengths and wiring delay. When constructing 3D systems, layer transfer technologies were important, especially those that supported reuse of the donor wafer and fabrication of active devices on the transferred layer.

Novelty and Inventive Step

Claims 1-20 were rejected on the ground of nonstatutory double patenting. The examiner stated that the claims were unpatentable over claims 1-20 of two different U.S. Patents. The examiner indicated that although the claims at issue are not identical, they are not patentably distinct from each other because the variations are obvious.

Claims

This patent contains 20 claims, with independent claims numbered 1, 8, and 15. The independent claims are generally directed to a semiconductor device comprising a first level with control circuits and a memory level disposed on top, bonded together with oxide-to-oxide and metal-to-metal bonding regions. The dependent claims generally add further details and limitations to the independent claims, such as specifying the thickness of the silicon layer, the type of memory, the number of sub-arrays, the connection of word lines, and the placement of memory cells relative to bonding regions.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
Array of memory cells
(Claim 1, Claim 8, Claim 15)		“In another aspect, a semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.”A structured arrangement of memory cells.
Control circuits
(Claim 1, Claim 8, Claim 15)		“In another aspect, a semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.”Electronic circuits that manage the operation of the memory cells.
Metal to metal bonding regions
(Claim 1, Claim 8, Claim 15)		“In another aspect, a semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.”Areas where metal layers are bonded together to join the first level and the memory level.
Oxide to oxide bonding regions
(Claim 1, Claim 8, Claim 15)		“In another aspect, a semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.”Areas where oxide layers are bonded together to join the first level and the memory level.
Word-lines
(Claim 8)		“In another aspect, a semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, and where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the array of memory cells include a plurality of word-lines (“WL”), and where at least one of said plurality of word-lines is directly connected to at least one of said metal to metal bonding regions.”Lines used to select specific memory cells within the array.

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US11621240

MONOLITHIC 3D INC
Application Number
US17949988
Filing Date
Sep 21, 2022
Status
Granted
Expiry Date
Sep 19, 2037
External Links
Slate, USPTO, Google Patents