3D Semiconductor Device And Structure

What is this patent about?

’222 is related to the field of 3D integrated circuits (3D-ICs) , specifically addressing challenges in their fabrication and performance. The background acknowledges that while transistor performance has improved with scaling, interconnect wiring performance has degraded, becoming a bottleneck. 3D stacking offers a solution by reducing wire lengths, but it introduces new problems, particularly heat removal and thermal management during fabrication.

The underlying idea behind ’222 is to improve the structure of 3D-ICs by optimizing the metal layer stack and via dimensions to enhance performance and power distribution. The key inventive insight is to use a relatively thick top metal layer (fifth metal layer) to act as a global power distribution grid , while also controlling the size of the vias connecting different layers. This addresses both the need for efficient power delivery and the challenges of fabricating high-density vertical interconnects.

The claims of ’222 focus on a semiconductor device with a layered structure. Specifically, the independent claims cover a device comprising a first silicon layer, multiple metal layers (first, second, third, fourth, and fifth), a second level containing transistors positioned above the third metal layer, and a via connecting through the second level. The claims emphasize a via diameter of less than 450 nm and a fifth metal layer significantly thicker (at least 50%) than either the third or fourth metal layers.

In practice, the invention aims to create a more robust and efficient 3D-IC. The thicker top metal layer serves as a dedicated power grid, ensuring stable voltage levels across the device, which is crucial for reliable operation. The small via size enables high-density vertical connections, allowing for more compact and complex 3D designs. The second level thickness being less than two microns further contributes to the device's compactness and potentially improves transistor performance.

This design differentiates itself from prior approaches by specifically addressing the power distribution challenges in 3D-ICs. Traditional approaches may not have optimized the metal layer thicknesses or via dimensions in this particular way. By using a thick top metal layer as a dedicated power grid and controlling via size, ’222 aims to provide a more efficient and reliable power delivery network, which is essential for the performance and stability of complex 3D integrated circuits. The use of tungsten in the via also suggests an emphasis on robust and reliable vertical interconnects.