Methods For Producing A 3D Semiconductor Device And Structure With Memory Cells And Multiple Metal Layers

What is this patent about?

’396 is related to the field of 3D semiconductor device fabrication , specifically focusing on methods for creating multilayer memory structures. The background involves the increasing demand for higher memory density and performance, which traditional 2D scaling struggles to meet. 3D integration offers a potential solution by stacking multiple layers of memory cells vertically, but this presents challenges in terms of fabrication complexity, thermal management, and process compatibility.

The underlying idea behind ’396 is to fabricate a 3D memory device by sequentially building multiple layers of memory cells on top of each other. This involves forming a base layer with metal interconnects, then adding subsequent layers where memory cells are patterned and etched. A key aspect is the shared gate electrode deposition step, where the gate electrodes for transistors in different memory layers are formed simultaneously. This simplifies the fabrication process and ensures consistent transistor characteristics across layers.

The claims of ’396 focus on a method for producing a 3D semiconductor device. This includes providing a base level with a single crystal layer, forming two metal layers for interconnect, and then creating at least two additional levels above these metal layers. The independent claims specify the formation of memory cells within these upper levels, using deposition and etching processes, and then forming gate electrodes for transistors in both levels in a single deposition step. Claim 1 requires the formation of at least four independent memory arrays, while claims 8 and 15 add limitations on the metal layer thicknesses and the gate electrode deposition method, respectively.

In practice, the method involves a sequential build-up of memory layers. A base layer, containing a single crystal silicon layer and metal interconnects, is first fabricated. Then, additional layers are added, each containing memory cells formed using transistors. The key is that the gate electrodes for transistors in different layers are deposited in a single step, which simplifies the fabrication process. This is achieved by carefully controlling the deposition and etching processes to ensure that the gate electrodes are formed simultaneously for transistors in different layers.

This approach differentiates itself from prior art by simplifying the fabrication process through the shared gate electrode deposition . Traditional methods often require separate gate electrode formation for each layer, which increases complexity and cost. By forming the gate electrodes simultaneously, ’396 reduces the number of processing steps and ensures consistent transistor characteristics across different memory layers. The use of Atomic Layer Deposition (ALD) for the gate electrode deposition, as specified in claim 15, further enhances the uniformity and conformality of the gate electrode layer.