IP Verse

Method For Producing A 3D Semiconductor Device And Structure With Memory Cells And Multiple Metal Layers

Patent No. US11862503 (titled "Method For Producing A 3D Semiconductor Device And Structure With Memory Cells And Multiple Metal Layers") was filed by Monolithic 3D Inc on Feb 7, 2023.

What is this patent about?

’503 is related to the field of 3D integrated circuit (3D IC) fabrication, specifically addressing methods for creating multilayer semiconductor devices. The background involves the increasing demand for higher density and performance in integrated circuits, leading to the exploration of 3D stacking as a solution. Traditional 3D IC fabrication faces challenges in mask-set costs and process complexity.

The underlying idea behind ’503 is to simplify the fabrication of 3D ICs by simultaneously forming gate electrodes for transistors located on different levels of the stack. This is achieved by performing a single deposition step that creates the gate electrodes for transistors in both the second and third levels of the 3D structure. This approach reduces the number of processing steps and potentially improves alignment between the gate electrodes.

The claims of ’503 focus on a method for producing a 3D semiconductor device. The method involves creating a multilayer structure with at least three levels. The key aspect is the simultaneous deposition of gate electrodes for transistors residing in the second and third levels. The structure includes metal layers for interconnection and single-crystal layers for transistor formation.

The implementation involves first creating a base level with a single-crystal layer and metal interconnects. Then, two additional levels are formed above, each containing memory cells with transistors. The inventive step is to deposit the gate electrodes for the transistors in these two levels in a single operation. This differs from prior approaches where each transistor layer would require its own separate gate electrode formation steps, potentially leading to misalignment and increased process complexity.

This simultaneous gate electrode deposition simplifies the manufacturing process and can improve the alignment accuracy between the gate electrodes and the transistor channels. The patent also mentions the use of Atomic Layer Deposition (ALD) for at least one of the deposition processes, which allows for precise control over the thickness and uniformity of the deposited layers. Finally, a through-layer via (TLV) connects the top metal layer to the second metal layer, enabling vertical communication within the 3D structure.

How does this patent fit in bigger picture?

Technical landscape at the time

In the early 2010s when ’503 was filed, 3D IC stacking was an area of active development, but at a time when true monolithic 3D integration, with sequential device fabrication on multiple levels, was still facing significant materials and process challenges. At that time, forming high-quality single-crystal silicon layers on top of metal layers, and then fabricating transistors within those layers, was non-trivial due to thermal budget limitations and the risk of damaging underlying circuitry.

Novelty and Inventive Step

The examiner approved the application because the prior art, whether considered individually or in combination, did not disclose or suggest all the claimed elements and limitations. Key limitations not found in the prior art include forming a second metal layer on top of a first metal layer, forming at least one second level disposed above the second metal layer, performing a first lithography step on the second level, forming at least one third level disposed above the second level, performing a second lithography step on the third level, forming memory cells in the second and third levels, and simultaneously depositing gate electrodes on transistors in both levels.

Claims

This patent contains 20 claims, with independent claims numbered 1, 8, and 15. The independent claims focus on methods for producing 3D semiconductor devices involving multiple levels, metal layers, lithography steps, and the formation of memory cells with transistors. The dependent claims generally elaborate on specific features, materials, or processing steps related to the methods described in the independent claims.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
First lithography step
(Claim 1, Claim 8, Claim 15)		“In one aspect, a method for producing a 3D semiconductor device, the method including: providing a first level, said first level comprising a first single crystal layer; forming a first metal layer on top of said first level; forming a second metal layer on top of said first metal layer; forming at least one second level disposed on top of or above said second metal layer; performing a first lithography step on said second level; forming at least one third level disposed on top of or above said at least one second level; and then performing a second lithography step on said third level; performing additional processing steps to form a plurality of first memory cells within said at least one second level and a plurality of second memory cells within said at least one third level, wherein said additional processing steps comprise deposition processes and etch processes, wherein each of said plurality of first memory cells comprises at least one second transistor, wherein each of said plurality of second memory cells comprises at least one third transistor; and then performing at least one deposition step that simultaneously deposits gate electrodes on both said second transistors and said third transistors.”A lithography step performed on the second level.
First metal layer
(Claim 1, Claim 8, Claim 15)		“In one aspect, a method for producing a 3D semiconductor device, the method including: providing a first level, said first level comprising a first single crystal layer; forming a first metal layer on top of said first level; forming a second metal layer on top of said first metal layer; forming at least one second level disposed on top of or above said second metal layer; performing a first lithography step on said second level; forming at least one third level disposed on top of or above said at least one second level; and then performing a second lithography step on said third level; performing additional processing steps to form a plurality of first memory cells within said at least one second level and a plurality of second memory cells within said at least one third level, wherein said additional processing steps comprise deposition processes and etch processes, wherein each of said plurality of first memory cells comprises at least one second transistor, wherein each of said plurality of second memory cells comprises at least one third transistor; and then performing at least one deposition step that simultaneously deposits gate electrodes on both said second transistors and said third transistors.”A metal layer formed on top of the first level (single crystal layer).
First single crystal layer
(Claim 1, Claim 8, Claim 15)		“In one aspect, a method for producing a 3D semiconductor device, the method including: providing a first level, said first level comprising a first single crystal layer; forming a first metal layer on top of said first level; forming a second metal layer on top of said first metal layer; forming at least one second level disposed on top of or above said second metal layer; performing a first lithography step on said second level; forming at least one third level disposed on top of or above said at least one second level; and then performing a second lithography step on said third level; performing additional processing steps to form a plurality of first memory cells within said at least one second level and a plurality of second memory cells within said at least one third level, wherein said additional processing steps comprise deposition processes and etch processes, wherein each of said plurality of first memory cells comprises at least one second transistor, wherein each of said plurality of second memory cells comprises at least one third transistor; and then performing at least one deposition step that simultaneously deposits gate electrodes on both said second transistors and said third transistors.”The initial layer of the 3D semiconductor device, made of a single crystal material.
Second lithography step
(Claim 1, Claim 8, Claim 15)		“In one aspect, a method for producing a 3D semiconductor device, the method including: providing a first level, said first level comprising a first single crystal layer; forming a first metal layer on top of said first level; forming a second metal layer on top of said first metal layer; forming at least one second level disposed on top of or above said second metal layer; performing a first lithography step on said second level; forming at least one third level disposed on top of or above said at least one second level; and then performing a second lithography step on said third level; performing additional processing steps to form a plurality of first memory cells within said at least one second level and a plurality of second memory cells within said at least one third level, wherein said additional processing steps comprise deposition processes and etch processes, wherein each of said plurality of first memory cells comprises at least one second transistor, wherein each of said plurality of second memory cells comprises at least one third transistor; and then performing at least one deposition step that simultaneously deposits gate electrodes on both said second transistors and said third transistors.”A lithography step performed on the third level.
Second metal layer
(Claim 1, Claim 8, Claim 15)		“In one aspect, a method for producing a 3D semiconductor device, the method including: providing a first level, said first level comprising a first single crystal layer; forming a first metal layer on top of said first level; forming a second metal layer on top of said first metal layer; forming at least one second level disposed on top of or above said second metal layer; performing a first lithography step on said second level; forming at least one third level disposed on top of or above said at least one second level; and then performing a second lithography step on said third level; performing additional processing steps to form a plurality of first memory cells within said at least one second level and a plurality of second memory cells within said at least one third level, wherein said additional processing steps comprise deposition processes and etch processes, wherein each of said plurality of first memory cells comprises at least one second transistor, wherein each of said plurality of second memory cells comprises at least one third transistor; and then performing at least one deposition step that simultaneously deposits gate electrodes on both said second transistors and said third transistors.”A metal layer formed on top of the first metal layer.

Patent Family

Patent Family

File Wrapper

The dossier documents provide a comprehensive record of the patent's prosecution history - including filings, correspondence, and decisions made by patent offices - and are crucial for understanding the patent's legal journey and any challenges it may have faced during examination.

  • Date

    Description

  • Get instant alerts for new documents

US11862503

MONOLITHIC 3D INC
Application Number
US18106757
Filing Date
Feb 7, 2023
Status
Granted
Expiry Date
Feb 28, 2031
External Links
Slate, USPTO, Google Patents