IP Verse

Dynamic Random Access Memory Applied To An Embedded Display Port

Patent No. US11894098 (titled "Dynamic Random Access Memory Applied To An Embedded Display Port") was filed by Wecrevention Inc on Mar 25, 2021.

What is this patent about?

’098 is related to the field of dynamic random access memory (DRAM), specifically addressing power consumption issues in embedded display port (eDP) applications. Modern eDPs often employ a panel self-refresh (PSR) function, which requires a frame buffer (typically DRAM) to maintain the display when the GPU is idle. While PSR reduces GPU power, the DRAM frame buffer's power consumption can offset these gains, creating a need for more efficient DRAM designs.

The underlying idea behind ’098 is to reduce the overall power consumption of a DRAM used in an eDP by operating its constituent blocks at different, lower voltages than typically specified by JEDEC standards. The key insight is that the memory core , the peripheral circuitry , and the input/output (I/O) interface can each function reliably at voltages below 1.1V, and that optimizing each block's voltage independently can minimize total power draw.

The claims of ’098 focus on a DRAM comprising a memory core, a peripheral circuit, and an I/O circuit, each operating at a different voltage. Specifically, the independent claims require that the peripheral circuit and the I/O circuit operate at voltages below 1.1V. Claim 1 further specifies that the memory core also operates below 1.1V, and that the core and peripheral circuits are on the same chip. Claim 6 requires that the DRAM is suitable for eDP applications.

In practice, this DRAM architecture allows for a more granular approach to power management. The memory core, responsible for data storage, might operate at a slightly higher voltage (though still below 1.1V) to maintain data integrity and performance. Meanwhile, the peripheral circuits, which handle tasks like address decoding and sensing, and the I/O circuits, which manage data transfer, can operate at lower voltages to minimize switching power, as these functions may not require the same performance headroom.

This approach differentiates from prior DRAM designs that adhere strictly to JEDEC voltage specifications, which often mandate higher voltages than necessary for all DRAM components. By decoupling the voltage requirements of different functional blocks and operating them at optimized, lower voltages, ’098 achieves a significant reduction in overall power consumption, making it particularly well-suited for power-sensitive eDP applications in portable devices.

How does this patent fit in bigger picture?

Technical landscape at the time

In the early 2010s when ’098 was filed, dynamic random access memory (DRAM) was commonly used as a frame buffer in timing controllers for liquid crystal displays, at a time when panel self-refresh (PSR) functionality was becoming more prevalent to reduce power consumption in graphic processing units (GPUs). At that time, reducing the power consumption of the timing controller itself, particularly the frame buffer, was a significant engineering constraint.

Novelty and Inventive Step

The examiner allowed the claims because the prior art did not teach or make obvious a DRAM comprising a core memory circuit, a peripheral circuit, and an input/output circuit, where the core memory cell circuit operates at a first voltage range lower than 1.1V, the peripheral circuit operates at a second voltage range lower than 1.1V, the input/output circuit operates at a third voltage range lower than 1.1V, the second voltage is different from the first voltage, and the third voltage is different from the first voltage.

Claims

The patent includes 9 claims, with independent claims 1, 2, 3, and 6. The independent claims generally focus on a dynamic random access memory (DRAM) comprising a DRAM core cell and a peripheral circuit or an input/output circuit, each operating at different voltage levels. The dependent claims generally add further limitations or features to the independent claims, such as specifying voltage levels or adding additional components.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
Dram core cell
(Claim 1, Claim 2, Claim 3, Claim 6)		“As shown in Table II, operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a first predetermined voltage, where the first predetermined voltage is lower than 1.1V; operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a second predetermined voltage, where the second predetermined voltage is lower than 1.1V; and operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.”A volatile memory cell within the DRAM that operates at a first voltage.
First voltage range
(Claim 1, Claim 2)		“As shown in Table II, operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a first predetermined voltage, where the first predetermined voltage is lower than 1.1V; operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a second predetermined voltage, where the second predetermined voltage is lower than 1.1V; and operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.”A range of voltage values within which the DRAM core cell operates, where the voltage is lower than 1.1V.
Input/output circuit
(Claim 3, Claim 6)		“As shown in Table II, operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a first predetermined voltage, where the first predetermined voltage is lower than 1.1V; operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a second predetermined voltage, where the second predetermined voltage is lower than 1.1V; and operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.”A circuit within the DRAM that is electrically connected to the DRAM core cell and operates at a third voltage lower than 1.1V.
Peripheral circuit
(Claim 1, Claim 2, Claim 3)		“As shown in Table II, operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a first predetermined voltage, where the first predetermined voltage is lower than 1.1V; operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a second predetermined voltage, where the second predetermined voltage is lower than 1.1V; and operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.”A circuit within the DRAM that is electrically connected to the DRAM core cell and operates at a second voltage lower than 1.1V.
Second voltage range
(Claim 1, Claim 2)		“As shown in Table II, operation voltages of the memory core unit 102 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a first predetermined voltage, where the first predetermined voltage is lower than 1.1V; operation voltages of the peripheral circuit unit 104 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a second predetermined voltage, where the second predetermined voltage is lower than 1.1V; and operation voltages of the input/output unit 106 in the DDR I specification, the low power DDR I specification, the DDR II specification, and the low power DDR II specification are a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.”A range of voltage values within which the peripheral circuit operates, where the voltage is lower than 1.1V.

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US11894098

WECREVENTION INC
Application Number
US17213133
Filing Date
Mar 25, 2021
Status
Granted
Expiry Date
Jun 19, 2033
External Links
Slate, USPTO, Google Patents