IP Verse

Chip Package

Patent No. US11894306 (titled "Chip Package") was filed by Piccadilly Patent Funding Llc As Security Holder on Nov 12, 2022.

What is this patent about?

’306 is related to the field of display technology and microelectronic packaging, specifically addressing the challenges of miniaturization and high-density interconnections in display devices. Traditional methods of connecting integrated circuits to display panels often suffer from performance limitations due to increased parasitic capacitance and resistance, especially as device dimensions shrink. The patent aims to improve electrical performance and reduce the overall size of display modules by using a glass substrate with through-glass vias (TGVs) for chip integration.

The underlying idea behind ’306 is to use a glass substrate as an interposer to bridge the connection between a display panel and integrated circuit chips. This involves creating metal conductors through the glass substrate (TGVs) and connecting these conductors to contact pads on the display panel using metal bumps. By embedding the metal conductors within the glass, the invention aims to minimize the distance between the chip and the display, thereby reducing parasitic effects and improving signal integrity.

The claims of ’306 focus on a chip package comprising a solid glass layer with metal posts in through-holes, an interconnection scheme on one surface, and a semiconductor chip connected to the metal posts. Specifically, the independent claims emphasize the arrangement of the metal posts near an edge of the glass layer, the composition of the interconnects (e.g., copper layers over other metal layers), and the connection of semiconductor chips to these interconnects and metal posts.

In practice, the invention involves fabricating a thin glass substrate with precisely positioned metal plugs or posts ( TGVs ) running through it. These TGVs act as vertical interconnects, allowing electrical signals to pass from one side of the glass substrate to the other. Semiconductor chips are then mounted on one side of the glass, with their contact pads aligned and connected to the TGVs. This arrangement allows for a very compact and efficient connection between the chips and the display panel.

The key differentiation from prior approaches lies in the use of glass as an interposer material and the extremely small distances maintained between the display area and the edge of the substrate. Glass offers a good CTE match to silicon, enhancing reliability, and the short distances minimize signal path lengths. This contrasts with traditional flip-chip packages that may use ceramic or plastic substrates, which can introduce larger parasitic effects and limit miniaturization. The ultra-thin profile and high-density interconnects enabled by the glass interposer are crucial for advanced display applications.

How does this patent fit in bigger picture?

Technical landscape at the time

In the early 2010s when ’306 was filed, microelectronic devices were being aggressively miniaturized, and flip-chip packaging was a common approach for high-density interconnections. At a time when systems commonly relied on solder bumps for connecting ICs to package media, challenges remained in areas such as thermal management and coefficient of thermal expansion (CTE) matching between different materials. Glass was being explored as an alternative interposer material, but forming through-glass vias (TGVs) and managing its lower thermal conductivity compared to silicon were non-trivial.

Novelty and Inventive Step

The examiner allowed the claims because the closest prior art does not disclose the specific material and structure of the claimed chip package. The examiner stated that the limitations related to forming a polymer interconnect with a sufficient coefficient of expansion to enable holes and other features formed inside with improved chemical durability, strength, and optical properties are material to the inventive concept. The dependent claims are allowable because they incorporate the limitations of the allowable independent claims.

Claims

This patent has 27 claims, with independent claims 1, 10, and 18. The independent claims are directed to chip packages comprising a solid layer, metal posts, interconnection schemes, metal bumps, and semiconductor chips. The dependent claims generally add specific details or features to the chip package described in the independent claims.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
First interconnection scheme
(Claim 1, Claim 10, Claim 18)		“As is well known, microelectronic devices have a tendency to be minimized and thinned with its functional development and a semiconductor package mounted on a mother board is also following the tendency in order to realize a mounting of high integration.”A structure over the first surface of the solid layer, comprising metal interconnects and a polymer layer, used for connecting to metal posts and semiconductor chips.
First metal bump
(Claim 1, Claim 10)		“Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads of chip and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path.”A bump comprising a metal layer and a tin-containing layer, located over the first interconnection scheme.
Metal posts
(Claim 1)		“Glass can be used as an interposer to bridge between one or more IC chips and a printed circuit board. In many respects, when used as an interposer/substrate and without the requirement for active devices, glass can be a good substitute for a silicon interposer. The advantages of glass in comparison to silicon as an interposer lie in its much lower material cost. Glass also has a CTE closely matched to silicon, so that reliability of interconnects, especially micro-bonds, can be expected to be quite good.”Conductive posts located within through holes in the solid layer's second region, facilitating electrical connections.
Solid layer
(Claim 1, Claim 10, Claim 18)		“Embodiments of the present disclosure provide A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps.”A layer composed of a silicon and oxygen compound, having a specified thickness and regions, used as a base for the chip package.
Through holes
(Claim 1, Claim 10, Claim 18)		“Glass has some disadvantages in comparison to silicon—notably its lower thermal conductivity and the difficulty in forming Through Glass Vias (TGV's). Both of these topics are discussed elsewhere in this patent.”Holes in the second region of the solid layer that contain the metal posts.

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US11894306

PICCADILLY PATENT FUNDING LLC AS SECURITY HOLDER
Application Number
US17985827
Filing Date
Nov 12, 2022
Status
Granted
Expiry Date
Sep 25, 2033
External Links
Slate, USPTO, Google Patents