Two-Color Self-Aligned Double Patterning (Sadp) To Yield Static Random Access Memory (Sram) And Dense Logic
Patent No. US11978639 (titled "Two-Color Self-Aligned Double Patterning (Sadp) To Yield Static Random Access Memory (Sram) And Dense Logic") was filed by Adeia Semiconductor Solutions Llc on May 23, 2023.
What is this patent about?
’639 is related to the field of semiconductor fabrication, specifically techniques for creating fin field-effect transistors (FinFETs) . These transistors are non-planar devices that offer improved performance compared to traditional planar MOSFETs, especially at smaller feature sizes. The patent addresses challenges in forming semiconductor fins with tight pitches, particularly in static random access memory (SRAM) and dense logic circuits, where variations in fin spacing and the presence of unwanted 'dummy' fins can negatively impact performance and manufacturability.
The underlying idea behind ’639 is to use a two-color self-aligned double patterning (SADP) process to create the fin structures. Instead of relying on a single lithography step followed by multiple spacer depositions and etches (as in self-aligned quadruple patterning, SAQP), this approach uses two separate lithography and etching steps, each with its own mask, to define different portions of the fin mandrel pattern. This allows for greater flexibility in controlling fin placement and spacing, and avoids the formation of unwanted dummy fins.
The claims of ’639 focus on a method of forming a semiconductor region by performing two lithography processes using two masks to form first and second mandrel patterns. Spacers are concurrently formed on the mandrels, and the mandrels are removed to form an intermediate fin pattern. The key aspect is that the resulting fin pattern has intentionally unequal fin pitches , or spacing, between adjacent fins. This is achieved by adjusting the relative placement and pitch of the two mandrel patterns.
In practice, the two-color SADP process involves first creating a pattern of mandrels using a first mask and etching process. Then, a second mask is used to create a second pattern of mandrels, which may have a different pitch or be offset relative to the first pattern. The two sets of mandrels are then used to define the fin pattern through spacer deposition and etching. By carefully designing the two masks, the resulting fin pattern can have regions with different fin pitches, allowing for optimized device performance and density. This is particularly useful in SRAM and dense logic circuits where some fins need to be closely spaced for performance reasons, while others need to be further apart to avoid unwanted interactions.
This approach differs from prior art SAQP methods, which often result in the formation of unwanted dummy fins due to the limitations of single-mask lithography at tight pitches. These dummy fins then require additional processing steps to remove, adding complexity and cost. By using two separate masks, ’639 avoids the formation of these dummy fins in the first place, simplifying the manufacturing process and improving yield. Furthermore, the ability to create variable fin pitches allows for greater flexibility in circuit design and optimization, enabling the creation of denser and higher-performance integrated circuits.
How does this patent fit in bigger picture?
Technical landscape at the time
In the late 2010s when ’639 was filed, semiconductor fabrication at advanced technology nodes was at a time when double or quadruple patterning techniques were commonly used to create features smaller than the resolution limits of available lithography equipment. At that time, sidewall image transfer processes were typically implemented using deposition and etching steps to form spacers that defined the critical dimensions of the fins. When forming dense structures like SRAM, hardware or software constraints made it non-trivial to avoid unwanted dummy fins, especially when variable fin pitches were required.
Novelty and Inventive Step
The examiner allowed the claims because prior art, specifically US Patent 10,096,587 to Yu et al., teaches performing a first lithography process using a first mask; forming first features comprising a first mandrel pattern based on the first lithography process; performing a second lithography process using a second mask; forming second features comprising a second mandrel pattern based on the second lithography process and concurrently forming spacers on first mandrels corresponding to the first mandrel pattern and second mandrels corresponding to the second mandrel pattern. The examiner considered this reference pertinent to the applicant's disclosure.
Claims
There are 25 claims in total, with independent claims 1 and 9 directed to methods of forming a semiconductor region using multiple lithography processes and mandrel/spacer techniques to create intermediate fin patterns. The dependent claims generally elaborate on the features, dimensions, and arrangements of the fins formed in the semiconductor region, as well as subsequent etching steps.
Key Claim Terms New
Definitions of key terms used in the patent claims.
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Date
Description
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US11978639
- Application Number
- US18201061
- Filing Date
- May 23, 2023
- Status
- Granted
- Expiry Date
- Dec 14, 2037
- External Links
- Slate, USPTO, Google Patents