Mitigating Surface Damage Of Probe Pads In Preparation For Direct Bonding Of A Substrate

Patent No. US11978681 (titled "Mitigating Surface Damage Of Probe Pads In Preparation For Direct Bonding Of A Substrate") was filed by Bank Of America Na on May 26, 2022.

What is this patent about?

’681 is related to the field of semiconductor device fabrication, specifically addressing challenges in preparing wafers for direct bonding after test probing. Test probes leave physical marks and protrusions on probe pads, disrupting the flatness required for successful direct bonding processes like wafer-to-wafer or die-to-wafer bonding. This is particularly relevant in advanced packaging techniques where precise alignment and strong bonding are crucial.

The underlying idea behind ’681 is to mitigate the impact of probe pad damage on direct bonding by either filling and planarizing the damaged areas, recessing the probe pads, or substituting a hybrid bonding layer for a conventional metallization layer. The goal is to restore a flat, uniform surface suitable for direct bonding, even after the probe pads have been physically disrupted during testing. This involves clever manipulation of metal and dielectric layers to create a planarized surface with suitable interconnects.

The claims of ’681 focus on structures and methods for creating a direct bonding surface on a semiconductor substrate after probe pads have been damaged during testing. The independent claims cover structures with buried probe pads, insulating layers, and operational interconnects arranged to facilitate direct hybrid bonding . They also cover methods of depositing insulating layers, patterning openings for interconnects, and planarizing the surface to achieve the required flatness for bonding.

In practice, the invention can be implemented in several ways. One approach involves depositing a metal layer over the damaged probe pads, planarizing it to create a flat surface, and then forming interconnects through a dielectric layer. Another approach involves recessing the probe pads into lower metallization layers, creating cavities that isolate the damaged areas from the bonding interface. A third approach replaces a conventional metallization layer with a hybrid bonding layer, eliminating the need for additional mask layers. These methods ensure that the protrusions from probe pad damage do not interfere with the direct bonding process.

Unlike conventional solutions that add sacrificial metallization layers, ’681 offers more efficient and cost-effective approaches. By either filling and planarizing, recessing the probe pads, or substituting a metallization layer with a hybrid bonding layer, the invention avoids the need for additional processing steps or materials. The use of liquid metal in recessed cavities for test probing is also a novel approach that prevents damage to the probe pads in the first place. These innovations improve the yield and reliability of direct bonding processes in advanced semiconductor packaging.

How does this patent fit in bigger picture?

Technical landscape at the time

In the late 2010s when ’681 was filed, semiconductor manufacturing processes were at a stage when direct bonding techniques were becoming increasingly important for advanced packaging. At a time when wafer-to-wafer and die-to-wafer bonding were typically implemented using oxide-oxide direct bonding or hybrid bonding, the planarity of the surfaces to be bonded was critical. When hardware or software constraints made it non-trivial to avoid probe pad damage during testing, alternative solutions were needed to ensure high bonding yields.

Novelty and Inventive Step

The examiner allowed the claims because the amended independent claims require operational interconnects on opposite lateral sides of the probe pad on a bonding surface, where both sides of the substrate are prepared for direct bonding using operational interconnects. The prior art only shows these interconnects on one lateral side of a probe pad or dummy interconnects on both lateral sides. The examiner considered that these amendments, in combination with the remaining claim limitations, made the claims allowable over the prior art.

Claims

There are 31 claims in total. Independent claims are claims 1, 11, 21, and 27. The independent claims generally focus on a structure, a bonded structure, a semiconductor device, and a method for direct hybrid bonding, respectively, all involving a buried probe pad. The dependent claims generally elaborate on the features and configurations described in the independent claims.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
Buried probe pad
(Claim 1, Claim 11)
“This disclosure describes methods and layer structures for mitigating surface damage of probe pads in preparation for direct bonding of a substrate, such as a reconstituted panel or the semiconductor substrate of a wafer or die. One example method prepares a semiconductor wafer for direct bonding processes by restoring a flat surface suitable for direct-bonding after disruption of probe pad surfaces during test probing.”A probe pad that is at least partially embedded in a dielectric material within a substrate, used for microelectronics and direct bonding.
Contact surface
(Claim 21)
“Test probing is routinely carried out on substrates, such as substrates of semiconductor materials, and on dies and reconstituted panels in microelectronics. Test probes make physical contact with probe pads on the given substrate. But the test probes can leave “probe marks” and surface disruption (“protrusions”), which can rise above the level of the dielectric passivation layer usually present around or above the probe pads.”The surface of the probe pad that comes into contact with a test probe, leaving a mark characteristic of the contact.
Direct hybrid bonding
(Claim 1, Claim 11, Claim 21, Claim 27)
“Direct bonding processes include techniques that accomplish oxide-oxide direct-bonding between dielectrics, and also include techniques that accomplish hybrid bonding, which can bond metal interconnects together in an annealing step of the same operation that direct-bonds the dielectrics together.”A bonding process that accomplishes oxide-oxide direct-bonding between dielectrics, and also bonds metal interconnects together in an annealing step.
Operational bonding pads
(Claim 27)
“One example method prepares a semiconductor wafer for direct bonding processes by restoring a flat surface suitable for direct-bonding after disruption of probe pad surfaces during test probing. The example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding.”Metal pads formed in openings on opposite lateral sides of a conductive pad, used to provide a surface for direct hybrid bonding.
Operational interconnects
(Claim 1, Claim 11)
“One example method prepares a semiconductor wafer for direct bonding processes by restoring a flat surface suitable for direct-bonding after disruption of probe pad surfaces during test probing. The example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding.”Interconnects that are part of a bonding surface prepared for direct hybrid bonding and are located on opposite lateral sides of the probe pad.

Litigation Cases New

US Latest litigation cases involving this patent.

Case NumberFiling DateTitle
7:25-cv-00511Nov 3, 2025Adeia Semiconductor Bonding Technologies Inc. v. Advanced Micro Devices, Inc.

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US11978681

BANK OF AMERICA NA
Application Number
US17825240
Filing Date
May 26, 2022
Status
Granted
Expiry Date
Apr 10, 2040
External Links
Slate, USPTO, Google Patents