Barrier Layers For Word Line Contacts In A Three-Dimensional Nand Memory And Fabrication Methods Thereof

What is this patent about?

’767 is related to the field of semiconductor memory, specifically three-dimensional (3D) NAND flash memory. The background involves increasing storage density by stacking memory cells vertically. A staircase structure is used to connect to the stacked word lines. As the number of stacked layers increases, forming reliable contacts to the word lines becomes challenging due to varying depths and potential over-etching during fabrication.

The underlying idea behind ’767 is to introduce a dual-layer barrier structure on the staircase to improve the etch-stop performance during contact formation. This involves using a first barrier layer to protect a second barrier layer from being etched during the word line formation process, and then using the second barrier layer as an etch stop during the contact formation process. A key aspect is selectively removing a portion of the second barrier layer near the gate line slit (GLS) to prevent unwanted conductive paths.

The claims of ’767 focus on a memory device comprising a film stack of alternating conductive and dielectric layers, a staircase structure, a dividing wall, a gate line slit (GLS), a first barrier layer on the staircase structure, and a second barrier layer on the first barrier layer in a specific region of the staircase structure. Crucially, the second barrier layer is positioned away from the GLS .

In practice, the invention involves depositing alternating layers of dielectrics, etching a staircase structure and a dividing wall, depositing a first barrier layer (e.g., silicon oxide), and then depositing a second barrier layer (e.g., silicon nitride). A block mask is used to selectively remove the second barrier layer near the GLS. This prevents the second barrier layer from being etched away during the subsequent removal of sacrificial layers to form the word lines, which could create unwanted conductive paths. Finally, contact openings are etched, using the second barrier layer as an etch stop, and filled with a conductive material to form the contacts.

This approach differs from prior solutions by introducing a selective removal step for the second barrier layer. Without this step, the second barrier layer, if made of the same material as the sacrificial layers, could be unintentionally removed during word line formation, leading to parasitic conductive paths and structural weaknesses. By strategically positioning and protecting the second barrier layer, the invention enables a more robust and reliable contact formation process in 3D NAND flash memory.