3D semiconductor device and structure with metal layers and memory cells

What is this patent about?

’737 is related to the field of multilayer or three-dimensional integrated circuits (3D ICs) and their fabrication. Specifically, it addresses the challenges of high mask costs, interconnect congestion, and the physical limitations of traditional through-silicon vias (TSVs) in complex semiconductor systems. The background context involves the need for higher integration density and lower power consumption in mobile and autonomous electronic devices.

The underlying idea behind ’737 is the construction of a vertically integrated system using multiple levels of single-crystal transistors and memory cells, where control and support functions are strategically separated into different layers. By utilizing layer transfer techniques, such as ion-cut, the invention allows for the stacking of high-performance monocrystalline silicon layers with extremely high vertical connection density. This enables the placement of memory control, clocking, or interface circuits on a base level while stacking multiple independent memory levels above it.

The claims of ’737 focus on a 3D semiconductor device featuring at least four distinct levels of transistors. The first level, built on a single-crystal layer, contains memory control circuits and specialized support circuitry—specifically Phase-Lock-Loop (PLL) or Digital-Lock-Loop (DLL) circuits, Serializer/Deserializer (SerDes) circuits, or a plurality of TSVs. The second and fourth levels contain memory cells, with the control logic in the first level managing the write operations for the memory cells located in the fourth level.

In practice, the invention works by fabricating a foundation layer with robust control logic and then transferring thin layers of single-crystal silicon to build subsequent tiers of transistors. This monolithic approach allows for through-layer vias (TLVs) with diameters significantly smaller than conventional TSVs, often less than 200 nm. This high-density vertical connectivity ensures that the memory control circuits on the bottom level can efficiently manage multiple tiers of memory cells stacked above, reducing the lateral area penalty typically associated with memory management logic.

This approach differs from prior art by overcoming the 'memory wall' and the alignment limitations of traditional wafer stacking. Unlike standard 3D integration that relies on large, area-consuming TSVs, the use of monolithic 3D stacking with layer transfer provides sub-micron alignment precision. This allows for the integration of disparate functions—such as high-speed logic, analog clocking, and dense memory—into a single, compact footprint with significantly reduced interconnect lengths and improved power efficiency.