Dynamic Random Access Memory Applied To An Embedded Display Port

What is this patent about?

’652 is related to the field of dynamic random access memory (DRAM), specifically addressing power consumption issues when DRAM is used as a frame buffer in embedded display port (eDP) applications. The background highlights the increasing power demands of timing controllers in eDP systems due to the inclusion of frame buffers for panel self-refresh (PSR) functionality, which aims to reduce overall system power by allowing the GPU to disconnect from the display panel when the displayed frame is static.

The underlying idea behind ’652 is to reduce the power consumption of DRAM used in eDP applications by operating different functional units of the DRAM at different, lower voltages than those specified by JEDEC standards. The key inventive insight is that the memory core , the peripheral circuitry , and the input/output (I/O) unit can each operate at voltages below 1.1V, optimizing power consumption for each unit individually.

The claims of ’652 focus on a DRAM comprising a DRAM core cell and an input/output circuit. The DRAM core cell operates at a first voltage, and the input/output circuit operates at a third voltage, where both the first and third voltages are lower than 1.1V. Claim 1 specifies that the DRAM core cell and the input/output circuit are formed on a single chip, the input/output circuit is external to the DRAM core cell, and the first voltage is different from the third voltage. Claim 3 specifies that the first voltage is greater than the third voltage, and the DRAM is capable to be applied to an embedded display port (eDP).

In practice, this architecture allows for a more efficient power distribution within the DRAM. The memory core, responsible for data storage, can operate at a voltage optimized for memory cell retention and access speed. The peripheral circuits, which handle control and refresh operations, and the I/O unit, responsible for data transfer to and from the DRAM, can operate at lower voltages, reducing power dissipation in these areas. This is particularly beneficial in eDP applications where the DRAM acts as a frame buffer, as it reduces both active and standby power consumption.

This approach differs from prior art DRAM designs that typically operate all functional units at the same voltage, often dictated by JEDEC standards. By independently controlling the voltage levels of the memory core, peripheral circuits, and I/O unit, ’652 enables a more granular power management strategy. This results in a DRAM that is better suited for low-power eDP applications, extending battery life in portable devices without sacrificing performance. The patent also suggests that the memory core could operate at 1.8V while the peripheral circuits and I/O operate below 1.1V, improving charge pump efficiency .