Heterogeneous Annealing Method And Device

What is this patent about?

’069 is related to the field of three-dimensional integrated circuits (3D ICs) , specifically addressing challenges in fabricating these circuits using direct wafer bonding. The background highlights the increasing demand for larger IC areas and more complex System-on-a-Chip (SoC) designs, which can lead to reduced yield and increased cost. Stacking and vertically interconnecting ICs offers a solution, but requires a cost-effective and manufacturable method for bonding and interconnection.

The underlying idea behind ’069 is to improve the reliability of direct bonding in 3D IC fabrication, particularly when dealing with dissimilar materials that have different coefficients of thermal expansion (CTEs). The core insight is that thinning one of the bonded wafers to accommodate CTE mismatch can compromise its stiffness, hindering the formation of reliable electrical interconnections. To counteract this, a third 'stiffening' wafer with a CTE similar to the other thick wafer is temporarily bonded to the thinned wafer to provide mechanical support during the heating process required for interconnection.

The claims of ’069 focus on a bonded structure comprising a thin first element (less than 100 microns) with insulating and contact regions directly bonded to a second element with corresponding regions. Critically, a third element is directly bonded to the thin first element, providing mechanical support. The third element is thicker than the first and has a coefficient of thermal expansion (CTE) similar (less than 1.0 ppm/°C difference) to the second element. The first element is sandwiched vertically between the second and third elements.

In practice, the method involves preparing two wafers for direct metal bonding, where the conductive metal portions may be recessed below the insulating portions. After bonding, one wafer is thinned to reduce CTE-induced stress during subsequent heating. However, this thinning reduces the wafer's stiffness. The third wafer, with a matching CTE, is then bonded to the thinned wafer, restoring the necessary stiffness to ensure proper contact and electrical interconnection between the metal portions during a heating step. This temporary stiffening allows for higher temperatures to be used without damaging the bond.

The key differentiation from prior approaches lies in the temporary use of a third wafer to provide mechanical support during the critical heating phase. Prior methods either did not address the stiffness issue of thinned wafers or relied on complex planarization techniques. By using a CTE-matched stiffening wafer, ’069 enables reliable 3D interconnection even with significant CTE mismatches between the primary bonded wafers, and without requiring extremely precise surface planarity. After the heating and interconnection process, the stiffening wafer can be removed, leaving a robust and electrically connected 3D structure.