Display Substrate And Display Device

What is this patent about?

’506 is related to the field of display technology, specifically addressing the design of a display substrate with an integrated gate driver on array (GOA) circuit. In modern displays, GOA circuits are used to sequentially activate gate lines, controlling pixel activation. A key challenge is maintaining stable output from the GOA circuit, especially during the 'keeping' phase where the output should remain constant despite noise and leakage currents. This is particularly important in displays using low-temperature polycrystalline oxide (LTPO) transistors, which require precise control to ensure consistent pixel charging.

The underlying idea behind ’506 is to improve the stability of the GOA circuit's output by incorporating a charge pump circuit within each shift register unit. This circuit, composed of capacitors and a transistor, boosts the potential of a critical node (the first node) during the keeping phase. By increasing the voltage level of this node, the transistor connected to it remains firmly on, effectively suppressing noise and maintaining a stable, low-voltage output signal. This ensures that the gate lines are reliably deactivated, preventing unwanted pixel activation and improving overall display quality.

The claims of ’506 focus on a display substrate featuring a shift register unit with a charge pump. The key elements include a first capacitor connected to a clock signal line and an input node, and a first transistor whose gate is connected to either its source or drain, forming a diode configuration. The claims emphasize the spatial arrangement of these components, requiring the first capacitor to be adjacent to the first transistor on the base substrate. Furthermore, the claims detail the connection of the transistor to the active layer through a via, ensuring that the channel region does not overlap with the via to avoid damage.

In practice, the charge pump circuit operates by using the clock signal to transfer charge to the first node, increasing its potential. The diode-connected transistor ensures that the charge remains trapped on the node, maintaining the boosted voltage during the keeping phase. The specific layout, with the capacitor adjacent to the transistor, is intended to minimize the area occupied by the circuit, allowing for a narrower bezel around the display. The use of a diode-connected transistor is a simple and effective way to achieve charge retention without requiring complex control circuitry.

A key differentiation from prior approaches lies in the specific configuration of the diode-connected transistor and the spatial arrangement of the capacitor and transistor. By ensuring that the via connecting the transistor to the active layer does not overlap with the channel, the patent aims to improve the reliability and performance of the transistor. The use of a three-capacitor structure connected in parallel further enhances the charge pumping capability, allowing for a more stable and noise-resistant output signal. This combination of circuit design and layout optimization contributes to a more robust and efficient GOA circuit for advanced display technologies.