Control Method And Controller Of 3D Nand Flash

Patent No. US12254925 (titled "Control Method And Controller Of 3D Nand Flash") was filed by Yangtze Memory Technologies Co Ltd on Feb 28, 2024.

What is this patent about?

’925 is related to the field of non-volatile memory, specifically 3D NAND flash memory. The background involves improving programming performance in these memories, which are used in various electronic devices. As memory density increases (MLC, TLC, QLC), the programming time becomes a critical factor, requiring efficient control of the number of programming voltage pulses.

The underlying idea behind ’925 is to optimize the programming process by adjusting the pulse widths of the programming voltage pulses applied to a memory cell. Instead of using uniform pulse widths, the invention proposes varying the pulse widths during the programming sequence, specifically making the last pulse wider than the preceding pulses.

The claims of ’925 focus on a method and a memory device that programs a memory cell by applying a sequence of pulses. This sequence includes a first pulse, middle pulses, and a last pulse. The key feature is that the last pulse has a wider pulse width than both the middle pulses and the first pulse. At least one of the middle pulses also has a pulse width wider than the first pulse.

In practice, this approach aims to reduce the overall programming time. By using a wider last pulse, the memory cell is given more time to reach the desired programmed state, potentially reducing the number of pulses needed. This is particularly relevant in 3D NAND flash, where programming time directly impacts read latency and overall system performance. The controller adjusts the waveforms to control the memory array.

This method differentiates itself from prior art by not using constant pulse widths for all programming pulses. Traditional methods increase the voltage of each pulse by a fixed amount (Vispp) while keeping the pulse width constant. ’925, however, introduces the concept of varying the pulse width , especially increasing the width of the final programming pulse, to achieve faster and more efficient programming. This allows for a narrower distribution of the threshold voltage Vt in the high state.

How does this patent fit in bigger picture?

Technical landscape at the time

In the early 2020s when ’925 was filed, 3D NAND flash memory was commonly used in various electronic devices, at a time when increasing memory density was typically achieved by adding more layers to the 3D structure. At this time, programming performance was a key consideration, and techniques to reduce programming time were actively being explored, when hardware or software constraints made precise control of programming voltage pulses non-trivial.

Novelty and Inventive Step

Claims were pending in the application. Claims 1-3, 5-7, 12-14, and 16-18 were rejected. Claims 4, 8-11, 15, and 19-20 were objected to. The Office action indicates that claim 1 was rejected for double patenting over U.S. Patent No. 11,948,641. The prosecution record does NOT describe the technical reasoning or specific claim changes that led to allowance.

Claims

This patent includes 20 claims, with independent claims 1 and 11. Independent claim 1 focuses on a method of programming a memory device, while independent claim 11 focuses on a memory device. The dependent claims generally elaborate on the specific details and variations of the method and device described in the independent claims, particularly relating to the pulse widths and programming voltages applied during the programming process.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
First program pulse
(Claim 1, Claim 11)
“summary, by adjusting the voltages of the plurality of the programming voltage pulses and the pulse widths of the plurality of the programming voltage pulses in the programming stage, the method and controller of the 3D NAND flash in the present application have advantages of reducing the programming voltage pulse counts in the programming process, which may reduce the programming time for the bit-cell of a 3D NAND flash memory array, so as to enhance programming performance.”The initial programming voltage pulse applied to a memory cell during a programming operation.
Last program pulse
(Claim 1, Claim 11)
“summary, by adjusting the voltages of the plurality of the programming voltage pulses and the pulse widths of the plurality of the programming voltage pulses in the programming stage, the method and controller of the 3D NAND flash in the present application have advantages of reducing the programming voltage pulse counts in the programming process, which may reduce the programming time for the bit-cell of a 3D NAND flash memory array, so as to enhance programming performance.”The final programming voltage pulse applied to the memory cell during a programming operation.
Middle program pulses
(Claim 1, Claim 11)
“summary, by adjusting the voltages of the plurality of the programming voltage pulses and the pulse widths of the plurality of the programming voltage pulses in the programming stage, the method and controller of the 3D NAND flash in the present application have advantages of reducing the programming voltage pulse counts in the programming process, which may reduce the programming time for the bit-cell of a 3D NAND flash memory array, so as to enhance programming performance.”Programming voltage pulses applied to the memory cell after the first program pulse and before the last program pulse.
Pulse width
(Claim 1, Claim 11)
“summary, by adjusting the voltages of the plurality of the programming voltage pulses and the pulse widths of the plurality of the programming voltage pulses in the programming stage, the method and controller of the 3D NAND flash in the present application have advantages of reducing the programming voltage pulse counts in the programming process, which may reduce the programming time for the bit-cell of a 3D NAND flash memory array, so as to enhance programming performance.”The duration of a programming voltage pulse.

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US12254925

YANGTZE MEMORY TECHNOLOGIES CO LTD
Application Number
US18590207
Filing Date
Feb 28, 2024
Status
Granted
Expiry Date
May 6, 2040
External Links
Slate, USPTO, Google Patents