Diffusion Barrier For Interconnects

Patent No. US12322650 (titled "Diffusion Barrier For Interconnects") was filed by Bank Of America Na on Sep 3, 2024.

’650 is related to the field of microelectronic packaging, specifically addressing challenges in 3D stacking of dies or wafers . Direct bonding techniques, like ZiBond or DBI, are used to stack these components, but misalignment of conductive interconnects during bonding can lead to performance degradation.

The underlying idea behind ’650 is to introduce a barrier interface between the conductive interconnects and the surrounding dielectric material (e.g., silicon oxide). This barrier inhibits the diffusion of conductive materials (e.g., copper) into the dielectric, which can occur due to misalignment and high-temperature annealing, ultimately preventing leakage and shorting.

The claims of ’650 focus on a bonded structure comprising a first substrate with a first insulating layer, an embedded barrier layer , a second insulating layer, and a first contact pad extending through these layers. The first substrate is directly bonded to a second substrate with a second contact pad, where the first and second contact pads are also directly bonded without adhesive.

In practice, the barrier interface can be implemented using materials with lower diffusivity for the conductive material than the surrounding dielectric, such as silicon nitride or aluminum oxide. Alternatively, the barrier can be an air gap or a roughened surface to prevent direct contact between the conductive interconnect and the dielectric. The width of the barrier is designed to be greater than the expected misalignment to ensure it intercepts any potential diffusion paths.

This approach differs from prior solutions by actively preventing diffusion rather than simply relying on precise alignment during bonding. By incorporating a diffusion barrier , the invention relaxes the accuracy requirements of pick-and-place tools, potentially increasing throughput in die-to-die and die-to-wafer bonding processes. The barrier also protects the dielectric from erosion during planarization, further enhancing reliability.

How does this patent fit in bigger picture?

Technical landscape at the time

In the late 2010s when ’650 was filed, dies or wafers were commonly stacked in three-dimensional arrangements for microelectronic packaging. At a time when direct bonding techniques were used to bond stacked dies or wafers, it was desirable that the surfaces of the dies or wafers to be bonded be extremely flat and smooth. When conductive interconnect structures from the respective surfaces are joined during bonding, misalignment could cause the conductive material of the overlaying interconnect pad to diffuse into the dielectric that it comes into contact with, potentially resulting in degraded performance of the microelectronic structure.

Novelty and Inventive Step

The examiner approved the application because the prior art does not teach or make obvious a bonded structure with a first substrate that includes an embedded barrier layer disposed on and extending parallel to the first insulating layer without extending below the upper surface of the first insulating layer, a second insulating layer disposed on and extending parallel to the embedded barrier layer, an upper surface of the second insulating layer forming part of the first bonding surface, and a first contact pad extending through the second insulating layer, through the embedded barrier layer, and at least partially through the first insulating layer; and a second substrate having a second bonding surface, the second substrate including an insulating material and a second contact pad, wherein the first bonding surface is directly bonded to the second bonding surface, and the first contact pad is directly bonded to the second contact pad, at a bonding interface without an intervening adhesive, in combination with other claimed features.

Claims

This patent includes 30 claims, with claims 1 and 14 being independent. The independent claims are directed to a bonded structure and a microelectronic assembly, respectively, both involving substrates directly bonded without adhesive and featuring embedded barrier layers. The dependent claims generally elaborate on the composition, configuration, and additional features of the elements described in the independent claims.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)	Support for Specification	Interpretation
Directly bonded (Claim 1, Claim 14)	“The first surface of the second substrate is bonded to the first surface of the first substrate without an intervening material such as an adhesive. When bonding stacked dies or wafers using a direct bonding technique, it is desirable that the surfaces of the dies or wafers to be bonded be extremely flat and smooth.”	A connection between two surfaces or structures achieved without the use of an intervening adhesive material.
Embedded barrier layer (Claim 1, Claim 14)	“The devices and techniques comprise the use of a barrier interface disposed generally between the conductive material and the dielectric that can inhibit the diffusion of the conductive layer into surrounding dielectric materials.”	A layer located within the first substrate, positioned between two insulating layers, and designed to prevent diffusion or other unwanted interactions between the contact pad and the surrounding insulating material.
First contact pad (Claim 1, Claim 14)	“Respective mating surfaces of the bonded dies or wafers often include embedded conductive interconnect structures, or the like. In some examples, the bonding surfaces are arranged and aligned so that the conductive interconnect structures from the respective surfaces are joined during the bonding. The joined interconnect structures form continuous conductive interconnects (for signals, power, etc.) between the stacked dies or wafers.”	A conductive structure within the first substrate that extends through multiple layers, including insulating and barrier layers, and is directly bonded to a corresponding contact pad on the second substrate.
First insulating layer (Claim 1, Claim 14)	“In an embodiment, a microelectronic assembly can include at least a first substrate having a first substantially planar surface, the first substrate comprising an insulating material or dielectric, for example. The dielectric may be provided on a base die or wafer of semiconductor, insulating, or conductive material.”	A layer of insulating material forming part of the first substrate, upon which the embedded barrier layer is disposed.
Second insulating layer (Claim 1)	“The substrates may be dies, wafers, carriers, large flat panels, or the like, comprised of a semiconductor or a non-semiconductor material. Semiconductor materials may, for example, comprise direct band gap or indirect band gap semiconductors and their combinations thereof. Non-semiconductor materials may comprise, for example, a dielectric material for example, glass, ceramic, silicon oxycarbides, silicon oxide, or the like, or combinations thereof.”	A layer of insulating material forming part of the first substrate, disposed on the embedded barrier layer, with its upper surface forming part of the first bonding surface.

Litigation Cases New

US Latest litigation cases involving this patent.

Case Number	Filing Date	Title
7:25-cv-00511	Nov 3, 2025	Adeia Semiconductor Bonding Technologies Inc. v. Advanced Micro Devices, Inc.

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US12322650

BANK OF AMERICA NA

Application Number: US18822980
Filing Date: Sep 3, 2024
Status: Granted
Expiry Date: Sep 27, 2038
External Links: Slate, USPTO, Google Patents

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