3D Semiconductor Devices And Structures With Metal Layers

What is this patent about?

’382 is related to the field of three-dimensional (3D) integrated circuits (ICs) and their fabrication. The background acknowledges that while semiconductor manufacturing has improved device density, the increasing mask set costs pose a challenge, especially for custom products. 3D stacking is presented as a solution to wire-related performance limitations in scaled ICs, offering shorter wire lengths and reduced wiring delay. Monolithic 3D technology, where multiple layers of transistors and wires are constructed monolithically, is a key approach.

The underlying idea behind ’382 is to create a multi-level semiconductor device by stacking transistor layers and memory arrays, leveraging layer transfer techniques to build a 3D structure. This involves bonding multiple levels of single-crystal silicon transistors, interconnected by metal layers, to achieve high density and performance. A key aspect is the use of a power delivery network within the metal layers to efficiently supply power to the stacked transistors and memory cells.

The claims of ’382 focus on a semiconductor device with multiple levels. Claim 1 specifies a device with four levels: a first level with single-crystal silicon transistors and I/O circuits, a second and third level with metal-gate transistors and memory arrays, and a fourth level with a second single-crystal silicon layer. The transistors are interconnected by metal layers, with the second metal layer serving as a power delivery network. A via connects the second and third levels. Other claims focus on the materials used for the metal gates, such as tungsten, and the lithography steps used to form the transistors.

The implementation involves fabricating multiple layers of transistors and memory cells, then stacking them using layer transfer techniques like ion-cut or SmartCut. The metal layers provide interconnection and power delivery, with vias connecting different levels. The use of metal gates, potentially including tungsten, in the transistors of the upper levels is a key feature. The power control circuits in the first level allow for efficient power management of the stacked transistors.

This approach differs from prior art by integrating multiple active device layers with memory arrays and a dedicated power delivery network, all fabricated using layer transfer. Unlike traditional 2D ICs, this 3D structure minimizes interconnect lengths and improves performance. The use of a foundation layer with pre-fabricated circuits, such as programming transistors or back bias voltage generators, further optimizes the design by separating high-voltage and high-performance functions. The precise alignment of metal layers and the use of small diameter vias are also critical for achieving high density and performance in the 3D structure.