IP Verse

Direct Hybrid Bonding Of Substrates Having Microelectronic Components With Different Profiles And/Or Pitches At The Bonding Interface

Patent No. US12381173 (titled "Direct Hybrid Bonding Of Substrates Having Microelectronic Components With Different Profiles And/Or Pitches At The Bonding Interface") was filed by Bank Of America Na on Dec 16, 2022.

What is this patent about?

’173 is related to the field of polishing integrated circuits, specifically chemical mechanical polishing (CMP) for hybrid bonding. Hybrid bonding is a technique used to bond microelectronic components, such as dies and wafers, forming electrical connections without adhesives. A key challenge in this process is achieving a planar surface on both the dielectric layers and the embedded conductive structures (e.g., copper pads) to ensure a strong and reliable bond. Conventional CMP techniques often result in dielectric erosion (rounding of the dielectric surface) and conductive structure dishing (recessing of the conductive structures), which can compromise the bond quality.

The underlying idea behind ’173 is to control the CMP process to minimize dielectric erosion and conductive structure dishing during the preparation of surfaces for hybrid bonding. This is achieved by carefully managing the material removal rates of the dielectric, barrier layer, and conductive structures during polishing. The key insight is to maintain a steady-state polishing process where the removal rates of these materials are balanced, resulting in a planar surface with minimal recessing of the conductive structures and minimal rounding of the dielectric.

The claims of ’173 focus on a component comprising two substrates directly hybrid bonded together. Each substrate has a dielectric layer and two pluralities of conductive structures with different profiles or pitches. The first and second substrates are bonded such that at least one conductive structure on each substrate is directly bonded to a corresponding conductive structure on the other substrate. The first dielectric layer at the bonding interface comprises a deposited layer including nitrogen. The claims emphasize the direct physical contact between copper structures on both substrates and the different profiles or pitches of the conductive structures.

In practice, the invention involves a multi-step CMP process. First, a dielectric layer is deposited and patterned on a substrate, creating openings. A barrier layer is then deposited over the dielectric and within the openings, followed by the deposition of a conductive structure. The conductive structure is then polished to expose the barrier layer, and the barrier layer is selectively polished to reveal the bonding surface of the dielectric. The polishing parameters, such as slurry composition, polishing pressure, and pad type, are carefully controlled to achieve the desired material removal rates and minimize dishing and erosion. The use of a reactive liquid slurry helps to maintain a uniform conductive structure removal rate.

The invention differentiates itself from prior approaches by focusing on achieving a steady-state polishing process and by using different profiles or pitches of conductive structures. Traditional CMP methods often result in excessive dishing and erosion due to uneven material removal. By carefully balancing the polishing rates and using specific pad layouts, the invention minimizes these defects, leading to a more reliable hybrid bond. The use of different profiles or pitches of conductive structures also allows for greater design flexibility and reduces the need for dummy pads, which can negatively impact signal integrity. The nitrogen-containing dielectric layer at the bonding interface further enhances the bond strength and reliability.

How does this patent fit in bigger picture?

Technical landscape at the time

In the early 2020s when ’173 was filed, hybrid bonding was an established technique for connecting microelectronic components, at a time when chemical-mechanical planarization (CMP) was typically used to prepare surfaces for bonding. Systems commonly relied on precise control of material removal rates during CMP to achieve the required planarity and feature dimensions, when hardware or software constraints made uniform polishing across the substrate non-trivial.

Novelty and Inventive Step

The examiner allowed the claims because of arguments and amendments made by the applicant, specifically addressing rejections under 35 USC 102. The examiner was persuaded by the applicant's arguments regarding drawing objections, leading to their withdrawal. The nonstatutory double patenting rejection was also rendered moot due to claim amendments. The examiner specifically noted the section "REMARKS" and "Rejections under 35 USC 102" in the applicant's amendment filed on November 20, 2024, as well as the "Allowable Subject Matter" section in the Office Action mailed August 27, 2024.

Claims

This patent contains 26 claims, with independent claims 1 and 16 directed to a component comprising first and second substrates with conductive structures. The dependent claims generally elaborate on the features, dimensions, materials, and arrangements of the conductive structures and substrates described in the independent claims.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
Directly hybrid bonded
(Claim 1, Claim 16)		“Hybrid bonding is a useful technique for bonding microelectric components such as dies and wafers and forming electrical connections. One hybrid bonding technique is “Direct Bond Interconnect (DBI®)” available from Invensas Bonding Technologies, Inc. (formerly known as Ziptronix, Inc.), a subsidiary of Xperi Corp. Generally, two dielectrics (located each on a separate substrate) are brought together to form a bond at low or ambient temperatures, without an intervening material such as an adhesive.”A bonding technique where two substrates are bonded directly to each other without an intervening adhesive layer, forming both a mechanical and electrical connection.
First conductive structures
(Claim 1, Claim 16)		“As part of, or subsequent to, this bonding process, a conductive structure (such as copper pads, posts, through substrate vias, or bumps) may be interspersed within the dielectric layers of the IC. Conductive features on each substrate may be aligned to provide an electrical interface between the two substrates. In the context of the present description, the term conductive structure may refer to a layer of any conductive material, and conductive structure dishing may refer to any dishing associated with the conductive structure or structures of interest.”Conductive structures that are part of a first plurality and are at least partially embedded in the first dielectric layer of the first substrate. They are directly bonded to third conductive structures on a second substrate.
First copper structure
(Claim 1)		“As part of, or subsequent to, this bonding process, a conductive structure (such as copper pads, posts, through substrate vias, or bumps) may be interspersed within the dielectric layers of the IC. Conductive features on each substrate may be aligned to provide an electrical interface between the two substrates. Further, the conductive structure may comprise materials such as copper, nickel, cobalt, gold, tin, and the like, and/or any alloy based on such elements.”A conductive structure made of copper, located on the second substrate, that is directly bonded to a second copper structure on the first substrate.
First dielectric layer
(Claim 1, Claim 16)		“A dielectric layer may include dielectric erosion (or a rounding of the surface of the dielectric layer), and a conductive structure may include dishing, both due to CMP, and both of which may negatively affect bonding. The disclosed techniques improve the planarization of the dielectric layer and the control of conductive structure dishing. The dielectric layer may comprise one or more layers of oxides, nitrides, or carbides of silicon, diamond, diamond like carbons (DLC), low dielectric constant material, glass, ceramic materials, glass ceramics, polymeric materials, and/or combinations thereof.”A layer of dielectric material that is part of the first substrate. It is directly bonded to a second dielectric layer of a second substrate.
Second conductive structures
(Claim 1, Claim 16)		“As part of, or subsequent to, this bonding process, a conductive structure (such as copper pads, posts, through substrate vias, or bumps) may be interspersed within the dielectric layers of the IC. Conductive features on each substrate may be aligned to provide an electrical interface between the two substrates. In the context of the present description, the term conductive structure may refer to a layer of any conductive material, and conductive structure dishing may refer to any dishing associated with the conductive structure or structures of interest.”Conductive structures that are part of a second plurality and are at least partially embedded in the first dielectric layer of the first substrate. They are directly bonded to fourth conductive structures on a second substrate.

Litigation Cases New

US Latest litigation cases involving this patent.

Case NumberFiling DateTitle
7:25-cv-00511Nov 3, 2025Adeia Semiconductor Bonding Technologies Inc. v. Advanced Micro Devices, Inc.

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US12381173

BANK OF AMERICA NA
Application Number
US18067617
Filing Date
Dec 16, 2022
Status
Granted
Expiry Date
Sep 17, 2038
External Links
Slate, USPTO, Google Patents