3D Processor Having Stacked Integrated Circuit Die
Patent No. US12401010 (titled "3D Processor Having Stacked Integrated Circuit Die") was filed by Bank Of America Na on Sep 14, 2021.
What is this patent about?
’010 is related to the field of three-dimensional integrated circuits, specifically addressing the increasing demand for higher transistor density in microchips. Traditional scaling approaches are reaching their physical limits, creating a need for alternative methods to improve performance and reduce power consumption.
The underlying idea behind ’010 is to vertically stack two or more integrated circuit dies, creating a 3D circuit where circuit blocks on different dies overlap and are electrically connected. This allows for shorter interconnects and higher bandwidth between functional units, such as processor cores and memory, compared to traditional planar designs.
The claims of ’010 focus on a 3D processor circuit comprising a first IC die with a processor core and a second IC die vertically mounted on the first, containing a cache for that core. The dies are connected through a hybrid bond with directly bonded metal contact pads and non-conductive regions, with the processor core electrically connected to the cache through these pads within the overlapping area.
This vertical stacking is achieved through direct bonding , such as hybrid bonding techniques like DBI, which allows for a high density of vertical connections (z-axis wiring) between the dies. These connections facilitate fast and efficient communication between the processor core and its cache, reducing latency and power consumption compared to traditional designs where these components are located on the same die.
By placing the cache directly above the processor core and using high-density vertical interconnects, the invention minimizes the distance signals need to travel, leading to improved performance and reduced power consumption. This approach contrasts with prior solutions that rely on longer, planar interconnects, which introduce greater resistance and capacitance, ultimately limiting performance.
How does this patent fit in bigger picture?
Technical landscape at the time
In the mid-2010s when ’010 was filed, at a time when integrated circuits were commonly being designed with increasing transistor density, stacking multiple dies vertically to create three-dimensional circuits was an area of active development. At that time, forming electrical connections between stacked dies using vertical interconnects was a non-trivial engineering challenge.
Novelty and Inventive Step
The examiner considered prior art (Ikegami et al. in view of Sadaka) but determined that it did not disclose, make obvious, or otherwise suggest the specific structure of the claimed invention, particularly the configuration of the IC dice, processor core, cache, overlapping area, hybrid bond, metal contact pads, and non-conductive regions, as recited in the claims.
Claims
This patent contains 26 claims, with independent claims numbered 1, 15, and 21. The independent claims generally focus on a three-dimensional processor circuit comprising two integrated circuit dies vertically mounted and interconnected via a hybrid bond, with one die containing a processor core and the other a cache. The dependent claims generally elaborate on specific features, configurations, and components of the 3D processor circuit and electronic device.
Key Claim Terms New
Definitions of key terms used in the patent claims.
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Date
Description
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US12401010
- Application Number
- US17474917
- Filing Date
- Sep 14, 2021
- Status
- Granted
- Expiry Date
- Jun 24, 2038
- External Links
- Slate, USPTO, Google Patents