Method for adjusting power consumption

What is this patent about?

’041 is related to the field of power management in mobile communication devices, specifically addressing the challenge of balancing high-performance processing needs with the limited energy capacity of batteries. In devices like smartphones or PDAs that handle diverse tasks—ranging from simple calendar updates to intensive video calls—fixed voltage and clock settings lead to significant energy waste during low-intensity operations. The background context involves the inherent relationship where power consumption scales with the square of the operating voltage, necessitating a dynamic approach to hardware resource allocation.

The underlying idea behind ’041 is the dynamic scaling of both the processor's clock frequency and its core operating voltage based on the specific performance requirements of the active software application. Rather than running the hardware at a constant maximum state to ensure the most demanding app functions correctly, the system identifies the 'performance class' of the current task and throttles the hardware down to the minimum necessary levels. This insight recognizes that non-real-time tasks can be executed at much lower energy states without degrading the user experience, significantly extending battery life.

The claims of ’041 focus on a dual-voltage architecture that enables stable frequency transitions by isolating the clock generation circuitry from the fluctuating core voltage. The system generates a first operating voltage that is adjustable to meet the processing demands of active applications, while simultaneously maintaining a second, constant operating voltage dedicated to the clock generation device, such as a phase-locked loop (PLL). This separation ensures that while the processor's supply is being ramped up or down to save power, the timing source remains stable and unaffected by potential voltage instability.

In practice, the invention utilizes a software-driven control loop where the operating system or a dedicated processor examines the performance needs of an application—such as a video call versus a text note—and writes a corresponding value to a control register. This digital value is converted into a reference voltage that dictates the output of a regulator supplying the processor core. To bridge the gap between the stable clock generator and the variable-voltage processor, a level shifter is employed to ensure the clock signals remain at the correct logic levels regardless of the current core voltage setting.

This approach differs from prior solutions that merely placed components into an inactive standby mode or used a single reference oscillator for all functions. By decoupling the clock generation power supply from the logic core power supply, the invention allows for seamless frequency and voltage transitions without requiring the system to halt or risk instability. This granular control allows the device to achieve up to 70% power savings during low-performance tasks, a feat impossible under traditional designs where the hardware is permanently tuned for worst-case scenarios.