Real-time I/O processor used to implement bus interface protocols

What is this patent about?

'071 is related to the field of bus interface protocols, specifically addressing the limitations of conventional protocol-specific and user-programmable interfaces. Traditional protocol-specific interfaces restrict a circuit to a single interface type, hindering marketability and adaptability. User-programmable interfaces, on the other hand, require manual intervention and lack the sophistication for complex signaling due to fixed wait states. These limitations create a need for a more flexible and adaptable interface solution.

The underlying idea behind '071 is to create a programmable interface that can act as a master device, controlling an external logic circuit. This is achieved by adding logic to a data storage element, such as a FIFO memory, enabling it to generate interface control signals like read and write signals, rather than simply responding to them. This allows a single processor architecture to be adapted for various design-specific devices and industry-standard protocols.

The claims of '071 focus on a circuit configured to store data and provide one or more control signals to an external device, with at least one of the control signals being a programmable clock signal. The claims also cover a method for providing a generic interface configured to control an external device, involving reading an instruction and performing an operation that includes either waiting a predetermined number of clock periods or branching based on signals received on a pin.

In practice, the invention uses a general-purpose interface (GPIF) to control FIFO blocks. The GPIF acts as a specialized I/O processor, generating waveforms for the FIFOs and waiting for external events. It develops a set of interface control signals in response to interface ready signals. The GPIF can initiate interrupts and resume operation based on processor signals, allowing for synchronized operations with external processors.

This approach differs significantly from prior solutions where external logic circuits acted as masters, providing control signals to slave data sources. By enabling the data interface to function as a master, the invention provides a more flexible and adaptable solution that can accommodate a variety of external logic devices. The programmability of the interface allows it to be configured for different bus interface protocols, minimizing the risk of interface errors and enabling efficient implementation of multiple industry-standard and customer-specific interfaces.