Semiconductor latches and SRAM devices

What is this patent about?

'689 is related to the field of static random access memory (SRAM), specifically addressing the challenge of increasing memory density and speed while minimizing power consumption. Traditional SRAM cells, built on single-crystal silicon, consume significant area, limiting density. Alternative approaches using polysilicon thin-film transistors (TFTs) offer higher density but suffer from lower performance.

The underlying idea behind '689 is to create a hybrid SRAM cell that leverages the strengths of both single-crystal silicon and TFT technologies. This is achieved by vertically stacking a high-performance inverter (for fast read/write operations) built on a high-mobility semiconductor layer (e.g., single-crystal silicon) with a lower-performance inverter (primarily for data retention) built on a lower-mobility semiconductor layer (e.g., polysilicon TFT).

The claims of '689 focus on a semiconductor latch comprising two back-to-back inverters formed on two separate semiconductor layers. One inverter, designed for high performance, is constructed on a high-mobility semiconductor layer. The other inverter, designed for lower performance, is constructed on a lower-mobility semiconductor layer. The two inverters are stacked vertically to reduce the latch area.

In practice, the high-performance inverter, typically implemented with CMOS transistors on single-crystal silicon, handles the data read and write operations, providing the necessary speed. The weaker TFT inverter, positioned above the CMOS inverter, maintains the data state with minimal power consumption. This vertical stacking significantly reduces the cell footprint compared to traditional planar SRAM designs, enabling higher memory densities.

This approach differentiates itself from prior solutions by combining the speed of single-crystal silicon with the density advantages of TFTs in a single SRAM cell. Unlike traditional SRAM cells that rely solely on single-crystal silicon, this hybrid design minimizes area consumption without sacrificing performance. Furthermore, by using a weaker TFT inverter for data retention, the cell's standby power consumption is significantly reduced compared to resistor-load or TFT PMOS-load SRAM cells.