Method for low temperature bonding and bonded structure

What is this patent about?

’987 is related to the field of semiconductor wafer bonding, specifically a method for achieving high-strength chemical bonds between materials at or near room temperature. Traditional bonding techniques often require high-temperature annealing, high pressure, or high voltage to convert weak van der Waals forces into strong covalent bonds. These conventional requirements can damage temperature-sensitive devices, introduce thermal stress, or cause misalignment between mismatched materials, creating a need for a more benign but effective bonding process.

The underlying idea behind ’987 is that a strong chemical bond can be initiated at room temperature by precisely controlling the surface chemistry and physical state of the bonding interface. The invention recognizes that by combining a very slight etch (VSE)—which activates the surface without degrading its planarity—with a specific chemical termination, the surfaces can be made highly reactive. This activation creates a defective or damaged zone just a few monolayers deep that facilitates the diffusion of reaction by-products, such as ammonia or hydrogen, away from the interface, thereby driving the formation of permanent covalent bonds without external heat.

The claims of ’987 focus on a multi-step surface preparation sequence that includes planarizing bonding layers to a high degree of smoothness, typically between 0.1 to 3 nm RMS, followed by a plasma reactive ion etch (RIE) to activate the surfaces. A critical aspect of the independent claims is the subsequent exposure of these etched surfaces to an ammonia-based solution or other terminating species. This chemical treatment populates the surface with specific groups, such as silanol or NH2, which are capable of spontaneous polymerization and chemical bond formation when the two surfaces are brought into direct contact in ambient conditions.

In practice, the method works by first depositing a polishable dielectric, like silicon oxide, over the irregular topography of a processed wafer. After the surface is made ultra-flat through chemical-mechanical polishing, the plasma RIE process cleans the surface and breaks atomic bonds to increase reactivity. The subsequent chemical dip ensures the surface is terminated with species that, upon contact with a mating surface, undergo a polymerization reaction. Because the process occurs at room temperature, it allows for the integration of disparate materials, such as InP, GaAs, or silicon, without the risk of thermal expansion mismatch causing the wafers to bow or slip.

This approach differentiates itself from prior art by moving away from the high-vacuum or high-temperature requirements of traditional fusion bonding. Unlike previous plasma treatments that merely charged the surface or relied on thick oxide growth, this invention utilizes a controlled defective zone to manage the kinetic by-products of the bonding reaction. By allowing these by-products to diffuse into the material or along the interface, the method achieves bonding energies comparable to bulk material fracture energy (up to 2500 mJ/m²) at temperatures as low as 25°C to 100°C, providing a robust pathway for 3D integrated circuit fabrication.