Method for fabricating semiconductor device
Patent No. US7365000 (titled "Method for fabricating semiconductor device") on Jun 28, 2004. The application was issued on Apr 29, 2008.
What is this patent about?
’000 is related to the field of semiconductor fabrication, specifically the creation of self-aligned contacts in high-density integrated circuits. As device dimensions shrink below 80nm, the aspect ratio between conductive structures like gate electrodes increases, making it difficult for traditional insulation materials to fill narrow gaps without leaving voids or suffering damage during subsequent wet cleaning steps.
The underlying idea behind ’000 is a hybrid insulation strategy that leverages the specific strengths of two different flowable materials to eliminate structural defects. By using a spin-on-glass (SOG) layer specifically for the narrow bottom gaps and an advanced planarization layer (APL) for the upper bulk insulation, the process avoids the micro-voids typical of APL in tight spaces while ensuring the SOG is thin enough to be fully densified during curing.
The claims of ’000 focus on a multi-stage fabrication sequence that includes forming conductive structures, depositing and curing a spin-on-glass layer, and then overlaying an advanced-planarization-layer to complete the composite insulation stack. The method specifically requires a wet cleaning step using a hydrofluoric acid (HF) or buffered oxide etchant (BOE) solution for a duration of 10 to 200 seconds to prepare the resulting contact holes.
In practice, the SOG layer is deposited with a controlled thickness that ensures the subsequent thermal curing process can penetrate and densify the material all the way to the bottom of the trench. This densification is critical because it provides the chemical resistance necessary to withstand the wet cleaning agents that would otherwise cause lateral erosion or 'pitting' in under-cured dielectric material.
This approach differentiates itself from prior methods by preventing the micro-voids that often form when APL is forced into high-aspect-ratio trenches, which can lead to electrical shorts or 'punches' during etching. By restricting the SOG to a thickness that allows for a complete cure, the invention provides a robust, planarized insulation stack that maintains structural integrity and precise contact dimensions even after aggressive chemical cleaning.
How does this patent fit in bigger picture?
Technical Landscape
In the early 2000s when ’000 was filed, semiconductor fabrication was transitioning toward sub-100nm design rules at a time when inter-layer dielectric gap-filling was typically implemented using high-temperature thermal flow processes like Borophosphosilicate Glass (BPSG). When systems commonly relied on these thermal processes, the resulting lateral diffusion of dopants often compromised the integrity of increasingly dense conductive patterns. As aspect ratios for gate electrodes increased, hardware constraints made achieving a void-free, chemically stable insulation layer non-trivial, forcing a shift toward flowable dielectrics such as Spin-on-Glass (SOG) or Advanced Planarization Layers (APL). However, these materials frequently exhibited non-uniform density or micro-voids, making them susceptible to structural failure or excessive erosion during subsequent wet cleaning and etching stages.
Prosecution Position
The disclosed invention represents a technical advancement through a hybrid architectural approach to inter-layer insulation that overcomes the density gradients inherent in single-layer dielectric applications. By integrating a cured SOG layer with a secondary APL layer prior to the self-aligned contact (SAC) etching process, the solution achieves a composite dielectric stack that maintains high gap-fill capability while mitigating the structural weaknesses of the individual materials. This specific integration enables the formation of high-aspect-ratio contact holes without the typical risks of inter-layer damage or 'punches' caused by micro-voids. The technical effect is a more robust insulation profile that withstands aggressive wet cleaning processes, ensuring reliable electrical isolation in ultra-fine pitch semiconductor devices.
Claims
The patent contains a total of 13 claims, with claim 1 serving as the sole independent claim. This independent claim focuses on a method for fabricating a semiconductor device that involves forming an insulation layer from a combination of spin-on-glass and advanced-planarization layers, followed by a specific contact hole cleaning process using a heavy water and fluorine oxide solution for a defined duration. The dependent claims serve to further specify the manufacturing parameters, such as the chemical composition of the source gases, the temperature and atmospheric conditions for curing, the specific materials used for conductive structures and etch stops, and the particular techniques employed for plug formation and self-aligned etching.
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US7365000
- Application Number
- US10876783A
- Filing Date
- Jun 28, 2004
- Publication Date
- Apr 29, 2008
- External Links
- Slate, USPTO , Google Patents