Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus

Patent No. US7373531 (titled "Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus") on May 5, 2005. The application was issued on May 13, 2008.

What is this patent about?

'531 is related to the field of power management in electronic devices, specifically addressing the problem of reducing power consumption in circuits that monitor the activity of other components, such as oscillators. The background involves wasteful power consumption in circuits like pre-scalers within Phase-Locked Loops (PLLs), where bias currents continue to flow even when the monitored signal is absent, leading to unnecessary energy dissipation.

The underlying idea behind '531 is to detect the presence or absence of a signal by monitoring the through current in a circuit comprised of a p-type and an n-type transistor connected in series, with the input signal applied to their gates. The key insight is that this through current only flows when the input signal is transitioning between high and low states. If the signal stops toggling, the through current ceases, indicating inactivity.

The claims of '531 focus on a signal detection method and device that uses the presence or absence of a through current in a CMOS-like structure (p-type and n-type transistors in series) to determine if an input signal is active. Specifically, the independent claims cover methods and devices for detecting the signal, determining if the signal is oscillating or static, detecting the frequency of the signal, and controlling power consumption based on the signal's activity.

In practice, the invention works by connecting the output of a component, such as an oscillator, to the gates of a series-connected p-type and n-type transistor pair. A current mirror circuit monitors the current flowing through this transistor pair. When the oscillator is running, the signal toggles, causing a brief through current to flow each time the transistors switch states. This through current is detected by the current mirror, indicating activity. If the oscillator stops, the through current stops, and after a predetermined time, a power consumption reduction signal is generated.

This approach differs from prior solutions that rely on detecting high or low states separately, which require more complex circuitry. It also avoids the slow response times associated with DC blocking capacitors used to detect signal stoppage. By directly sensing the switching activity through the through current, the invention provides a simple and efficient way to determine if a signal is present and oscillating, enabling a quick and reliable power-saving mechanism.

How does this patent fit in bigger picture?

Technical Landscape

In the mid-2000s when ’531 was filed, power management in integrated circuits was typically implemented using dedicated monitoring logic that often required continuous bias currents, even during idle states. At a time when systems commonly relied on external oscillators or phase-locked loops to drive signal processing, hardware constraints made the detection of signal presence or frequency non-trivial without introducing additional power overhead. Engineering practices of this era frequently utilized CMOS-based architectures where through currents were viewed as a parasitic loss to be minimized, rather than a functional metric for state detection.

Prosecution Position

Following the filing of this application, the examiner issued a non-final Office Action rejecting all pending claims. Specifically, claims were rejected under 35 U.S.C. § 112 for indefiniteness and under 35 U.S.C. § 102 and § 103 as being anticipated by or obvious over prior art references. The prosecution record indicates that the application later proceeded to allowance; however, the provided record does not describe the specific technical reasoning or claim changes that led to that allowance.

Claims

This patent contains 13 claims, of which claims 1, 2, 4, 5, 6, 7, 9, 10, and 11 are independent. The independent claims are generally directed to methods and devices for signal detection, frequency detection, and power consumption control based on detecting a through current in a circuit. The dependent claims generally add further limitations or details to the independent claims, such as specifying transistor configurations.

Key Claim Terms New

Definitions of key terms used in the patent claims.

Term (Source)Support for SpecificationInterpretation
First state
(Claim 2, Claim 5, Claim 7, Claim 10, Claim 11)
In the present invention, a signal inputted to the input terminal is applied to the gates of a p-type transistor and an n-type transistor connected in series, such as CMOS, for example, to detect a through current flowing through the p-type transistor and n-type transistor, and when the through current is detected, the signal is determined as being in the first state in which the signal repeatedly goes to a high level and a low level alternately, while when the through current is not detected in a predetermined period of time, the signal is determined as being in the second state in which the signal is kept at a high level or a low level.A state in which the signal repeatedly goes to a high level and a low level alternately.
N-type transistor
(Claim 1, Claim 4, Claim 6, Claim 9)
In the present invention, a signal inputted to the input terminal is applied to the gates of a p-type transistor and an n-type transistor connected in series, such as CMOS, for example, to detect a through current flowing through the p-type transistor and n-type transistor. Since the through current is generated at an intermediate potential between potentials at which ON/OFF of the p-type transistor and n-type transistor is switched, it is generated when the signal switches to a low level from a high level, or switches to a high level from a low level.A type of transistor used in a circuit, where the signal is inputted to its gate. It is connected in series with a p-type transistor.
P-type transistor
(Claim 1, Claim 4, Claim 6, Claim 9)
In the present invention, a signal inputted to the input terminal is applied to the gates of a p-type transistor and an n-type transistor connected in series, such as CMOS, for example, to detect a through current flowing through the p-type transistor and n-type transistor. Since the through current is generated at an intermediate potential between potentials at which ON/OFF of the p-type transistor and n-type transistor is switched, it is generated when the signal switches to a low level from a high level, or switches to a high level from a low level.A type of transistor used in a circuit, where the signal is inputted to its gate. It is connected in series with an n-type transistor.
Second state
(Claim 2, Claim 5, Claim 7, Claim 10, Claim 11)
In the present invention, a signal inputted to the input terminal is applied to the gates of a p-type transistor and an n-type transistor connected in series, such as CMOS, for example, to detect a through current flowing through the p-type transistor and n-type transistor, and when the through current is detected, the signal is determined as being in the first state in which the signal repeatedly goes to a high level and a low level alternately, while when the through current is not detected in a predetermined period of time, the signal is determined as being in the second state in which the signal is kept at a high level or a low level.A state in which the signal is kept at one of a high level and a low level.
Through current
(Claim 1, Claim 2, Claim 4, Claim 5, Claim 6, Claim 7, Claim 9, Claim 10, Claim 11)
In the present invention, a signal inputted to the input terminal is applied to the gates of a p-type transistor and an n-type transistor connected in series, such as CMOS, for example, to detect a through current flowing through the p-type transistor and n-type transistor. Since the through current is generated at an intermediate potential between potentials at which ON/OFF of the p-type transistor and n-type transistor is switched, it is generated when the signal switches to a low level from a high level, or switches to a high level from a low level. Therefore, the presence or absence of an input signal can be detected based on the presence or absence of the through current.A current flowing through a circuit to which a signal is inputted. The presence or absence of this current is used to detect the input of a signal, the frequency of a signal, or the state of a signal (alternating between high and low levels, or remaining at a high or low level).

Litigation Cases New

US Latest litigation cases involving this patent.

Case NumberFiling DateTitle
1:25-cv-00323Mar 14, 2025Riddell, Inc. V. Certor Sports, Llc

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US7373531

Application Number
US11122123A
Filing Date
May 5, 2005
Publication Date
May 13, 2008
External Links
Slate, USPTO, Google Patents