Modulation of signals for transmission in packets via an air interface

What is this patent about?

’872 is related to the field of wireless communication and signal modulation, specifically within the context of short-range radio links like Bluetooth. In these systems, data is transmitted in packets containing different functional sections, such as synchronization codes, headers, and payloads. Traditional systems often face a trade-off between increasing data rates and maintaining backward compatibility with older hardware that expects a specific, simpler modulation format for packet synchronization.

The underlying idea behind ’872 is that a single, higher-order modulation scheme can be used to transmit data at different rates by restricting the available symbol space for specific parts of a packet. Instead of switching between two entirely different modulation methods—which would require complex guard times and re-synchronization—the system uses a constrained subset of a complex modulation scheme for the packet header and a full set of values for the payload. This allows the header to remain readable by legacy devices while the payload carries data at a much higher density.

The claims of ’872 focus on a modulation method and hardware that maps data to symbols based on a selected scheme, where a first plurality of bits is modified by adding a fixed-value bit to create bit pairs. By forcing one bit in a pair to a constant value (e.g., always '0'), the modulator effectively limits the resulting signal to a smaller set of possible phase changes or states. The claims specifically cover the transition between this restricted mapping for one part of the packet and a standard mapping for the second plurality of bits, where all bits are variable.

In a practical implementation using π/4-DQPSK, the system achieves higher throughput by treating the payload as a series of two-bit symbols, allowing for four possible phase shifts. However, for the access code and header, the inventor proposes 'freezing' one bit of each pair. This forces the modulator to only output two specific phase shifts (such as +45° and -45°), which mimics the behavior of simpler GFSK modulation. Because the underlying waveform remains consistent, the hardware does not need to pause or reset its clock when moving from the header to the high-speed payload.

This approach differentiates itself from prior art by eliminating the need for guard times or dedicated re-synchronization sequences between different packet entities. By using a single modulator that simply changes its bit-mapping logic on the fly, the invention maintains full backward compatibility with legacy receivers while doubling the effective user data rate. It essentially tricks older devices into seeing a compatible synchronization signal while providing modern devices with the full bandwidth of the advanced modulation scheme.