Memory module decoder

What is this patent about?

’912 is related to the field of high-density memory modules, specifically those utilizing double-data-rate (DDR) dynamic random-access memory (DRAM) devices. In modern computing, memory controllers are often limited by the number of physical ranks or chip-select signals they can support, which in turn restricts the total memory capacity available per slot. The invention addresses the need to bypass these hardware limitations by allowing a computer system to interface with a high-capacity module as if it were a standard, lower-density component.

The underlying idea behind ’912 is the implementation of a virtual memory architecture where a logic element acts as an intermediary between the host computer and a larger-than-expected array of memory devices. By intercepting standard control signals—such as chip-selects and address bits—the logic element performs rank multiplication or density simulation. This allows the system to address a greater number of physical memory ranks than the memory controller is natively configured to handle, effectively tricking the BIOS into seeing a single high-density rank where multiple lower-density ranks actually exist.

The claims of ’912 focus on a memory module comprising a printed circuit board populated with a plurality of DDR memory devices arranged in a first number of ranks, managed by a circuit containing a logic element, a register, and a phase-lock loop (PLL). The independent claims specifically cover the mechanism where the logic element receives a set of input signals (chip-selects, bank addresses, and row/column addresses) corresponding to a smaller number of ranks and translates them into a larger set of output signals that control the actual, higher number of physical ranks. This translation includes responding to host commands by selectively activating specific ranks or pairs of ranks to ensure the module behaves as a unified, higher-capacity entity.

In practice, the invention works by using the logic element to re-map address and command signals in real-time. For example, an extra row address bit from the host can be converted into a column address bit or used to toggle between physical ranks that the host cannot see. To maintain signal integrity during these complex operations, the module utilizes a PLL for precise clock distribution and a register to buffer control signals. The invention also describes methods for managing data strobe (DQS) signals, such as using isolation switches or current-limiting resistors to prevent signal collisions when multiple physical devices are tied to a single logical data path.

This approach differs from prior solutions by moving the complexity of rank management off the motherboard and onto the module itself. Traditional modules are limited by the fixed number of chip-select lines provided by the memory controller; however, ’912 enables density multiplication without requiring hardware changes to the host system. By reporting a virtual configuration through the Serial Presence Detect (SPD) device, the module ensures compatibility while utilizing lower-cost, lower-density DRAM components to achieve high-capacity results that would otherwise be economically or technically unfeasible.