Method and system for automatically calibrating intra-cycle timing relationships for sampling signals for an integrated circuit device

What is this patent about?

’835 is related to the field of high-speed digital signaling and memory interface timing. Specifically, it addresses the challenges of maintaining signal integrity in Double Data Rate (DDR) memory systems, where shrinking timing margins and physical variations in printed circuit boards or silicon fabrication can lead to intermittent data errors or total system failure.

The underlying idea behind ’835 is that a system can achieve reliable high-speed operation by autonomously discovering its own functional timing windows rather than relying on pre-defined, static specifications. By treating the phase relationships between different signal classes as variables in a multi-dimensional configuration space, the system can map out a valid operation range through active experimentation, effectively compensating for environmental drift and manufacturing tolerances.

The claims of ’835 focus on a systematic method for calibrating intra-cycle timing by independently and sequentially shifting the phases of three distinct signal groups: command signals, data signals (DQ), and sampling signals (DQS). The process involves generating access commands and then iteratively adjusting the phase shifts of these signals to identify the boundaries of a functional operating region, ultimately selecting an optimal operation point within those boundaries.

In practice, the invention utilizes a delay calibrator integrated into a memory controller to perform a two-stage search. It first executes a coarse calibration by varying parameters in large increments to quickly locate the general vicinity of a functional window, followed by a fine-grained, univariate search to pinpoint the exact edges of the timing margin. This is achieved by writing and reading back test data to verify which phase combinations result in error-free transmission.

This approach differs from prior solutions that typically required a known-stable initial state or relied on rigid timing specifications that could not adapt to poor-quality hardware. By exploring the configuration space without a-priori knowledge of a stable point, the invention allows for the use of components or circuit boards that might otherwise be deemed inoperable, effectively creating extra margin where traditional fixed-timing designs would fail.