Non-volatile memory module

What is this patent about?

’833 is related to the field of memory modules and data preservation systems, specifically addressing the challenge of maintaining data integrity in volatile memory during power interruptions. In high-performance computing, volatile memory like DRAM provides high-speed access but loses data without power, while non-volatile memory like NAND flash is persistent but slower. The background context involves the need for a reliable, maintenance-free backup mechanism that can bridge these two memory types without the environmental and reliability drawbacks of traditional battery-backed systems.

The underlying idea behind ’833 is to implement a hybrid memory architecture that dynamically adjusts its operational parameters to facilitate an emergency data transfer from volatile to non-volatile storage. The key inventive insight is the use of a variable clock frequency strategy during backup and restore operations. By down-clocking the volatile memory subsystem to a frequency lower than its standard host-facing speed, the system reduces peak power consumption and aligns the data throughput more closely with the slower non-volatile storage, allowing the entire backup process to be sustained by a compact, non-battery power source like a capacitor array.

The claims of ’833 focus on a control method and system architecture that manages three distinct clock frequencies across two modes of operation. Specifically, the independent claims cover a memory system that operates the volatile subsystem at a high first frequency for host communications, but switches to a significantly lower third frequency when entering a backup mode. This backup mode involves moving data between the volatile and non-volatile subsystems, with the non-volatile side operating at its own specific second frequency, ensuring that the volatile memory is not running at full speed when the host is no longer the primary interface.

In practice, the invention utilizes a controller, such as an FPGA, to monitor for trigger conditions like a power failure. When a failure is detected, an isolation circuit decouples the volatile memory from the host to prevent signal interference and capacitive loading. The system then transitions to a secondary power state where the capacitor bank provides the necessary energy to flush the volatile data into the flash memory. To further optimize power, the controller can perform data slicing, activating only specific segments of the memory bus at a time while keeping the remaining segments in a low-power self-refresh state.

This approach differs from prior solutions by eliminating the reliance on bulky batteries and providing a more granular control over the memory's power profile. Unlike standard backup systems that attempt to run the memory at its rated speed until power is exhausted, this invention recognizes that the bottleneck during a backup is the non-volatile write speed. By intentionally slowing down the volatile memory's clock and using frequency-divided signals, the system extends the effective life of the stored capacitive charge, ensuring a complete and reliable data transfer even in space-constrained server environments.