Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches

What is this patent about?

’253 is related to the field of memory management in computing systems, specifically addressing the overhead associated with context switching in virtualized environments. In traditional systems, switching between different operating systems or applications often requires flushing the Translation Lookaside Buffer (TLB) or virtually tagged caches to prevent address aliasing. This flushing process significantly degrades performance by forcing the system to reload memory mappings from slower main memory after every switch.

The underlying idea behind ’253 is to eliminate the need for frequent cache flushes by embedding multi-level ownership metadata directly into each cache or TLB entry. By tagging entries with both a specific application context ID and a broader virtual machine ID, the hardware can distinguish between memory pages that belong to a specific process and those that are shared globally across a virtual machine. This allows entries from different virtual worlds to coexist in the hardware simultaneously, maintaining isolation without sacrificing speed.

The claims of ’253 focus on a hardware matching circuit that evaluates multiple context identifiers in parallel to determine a cache hit. Specifically, the independent claims describe a mechanism where a cache entry stores at least two distinct context IDs and a selecting value or logic gate (such as an OR gate). During a search, the hardware compares the stored IDs against provided system IDs and uses the selecting logic to validate the entry based on whether it is marked as a local process-specific page or a global machine-wide page.

In practice, the invention works by extending the standard tag comparison logic with additional comparators and multiplexers. When the CPU performs a memory lookup, it doesn't just check the virtual address; it also checks the current VM ID and App Context ID against the tags in the cache. If an entry is marked as 'global' for a virtual machine, the hardware ignores the specific application ID and grants a match based on the machine ID alone. This ensures that shared kernel pages or hypervisor resources remain resident in the cache even as the system toggles between different user applications.

This approach differs from prior solutions by moving the management of 'global' status from a single bit to a flexible, hierarchical tagging system. While older systems might have a single global bit that applies to everyone, this invention allows for 'nested' global status—pages can be global to one virtual machine but invisible to another. Furthermore, by using multiplexers to switch between code and data context IDs, the architecture provides a granular way to handle different translation domains without the performance penalty of a total pipeline flush.