Method and apparatus for optimizing driver load in a memory package

What is this patent about?

’060 is related to the field of high-density memory systems, specifically focusing on the architecture of three-dimensional stacked (3DS) memory packages. In traditional stacked memory, multiple array dies are connected to a single vertical interconnect, creating a significant capacitive load that requires large, power-hungry drivers on the control die. As memory density increases and physical dimensions shrink, this parasitic loading becomes a bottleneck for both power efficiency and signal integrity, limiting the overall speed and performance of the memory module.

The underlying idea behind ’060 is to reduce the electrical load on individual drivers by partitioning the vertical interconnects into multiple, isolated segments. Instead of a single bus connecting all dies in a stack to one driver, the invention splits the dies into distinct groups, each served by its own dedicated die interconnect and corresponding driver on the control die. By distributing the total stack capacitance across several smaller conduits, the system can utilize smaller, faster drivers that consume less power while maintaining high signal quality across the entire stack.

The claims of ’060 focus on a memory package architecture where a plurality of stacked array dies are divided into at least two exclusive groups. A first die interconnect is electrically coupled only to the first group, while a second die interconnect is coupled only to the second group. A control die manages these paths through a multi-conduit data path connected to a single external data terminal. The control die includes logic to selectively activate the specific driver and interconnect path required to reach a target die based on incoming chip-select and control signals.

In practice, this mechanism functions as a load-balancing system within the package. When the memory controller targets a specific die, the control die identifies which group that die belongs to and enables only the relevant data conduit. Because each driver only 'sees' the capacitance of a subset of the dies and a shorter effective length of the vertical via, the transition times are improved. This architecture allows the package to appear as a single-die load to the external system bus while internally managing a complex, high-capacity stack.

This approach differs from prior solutions that relied on a single, heavily loaded through-silicon via (TSV) for all dies in a stack. By implementing selective isolation at the interconnect level, the invention avoids the latency penalties and signal degradation inherent in driving a large number of parallel loads. Furthermore, the control die is designed to be versatile, supporting both standard registered DIMM operations and advanced 3DS modes, effectively bridging the gap between high-capacity storage and high-speed data transfer requirements.